Hello Guys,
I am working with Synplify Pro. I have a RTL wrapper in Verilog where a module is instantiated. But this module is available as an EDF netlist. How can I include this EDF netlist in my Synplify project so that it can be integrated with the wrapper RTL without any compilation error?
Best regards, Rahul
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How
Just add a blackbox synthesis directive to the wrapper and everything will be fine.
Jon
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l
Additionally, IO insertion should be disabled when the EDIF netlist is generated. If IO insertion isn't disabled, Synplify Pro treats the inputs and outputs on the RTL used for edif netlist as IOs and instantiates IO pads on it.
Thanks Shyam
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