regarding specifying clock as internal signal in chipscope

Hi all, i am using chipscope for checking the behavior of the internal signals, i have a problem my differential clock and data input is coming form the other board. i am just taking the differnential clock and making into single ended clock usign IBUFGDS and then taking that internal single ended clock signal for data processing.

what i wnated to make sure is that clock is pure clock sicne i am recieving form the external board. so that while processing with the input data the it must be synchronous and meet all the setup and hold time volation. so i wnated to view it in chipscope. but i am unable use this clock internal signal while i am inserting for "chipscope pro inserter" for clock port and i wnated to see the datain (its also the internal signal form the differntial signal) whether it is meeting the constraints. how can i specify them in the chipscope inserter.

what kind of signal i should make as trigg ports. thanks

regard srik

Reply to
ekavirsrikanth
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Hi all, i am using chipscope for checking the behavior of the internal signals, i have a problem my differential clock and data input is coming form the other board. i am just taking the differnential clock and making into single ended clock usign IBUFGDS and then taking that internal single ended clock signal for data processing.

what i wnated to make sure is that clock is pure clock sicne i am recieving form the external board. so that while processing with the input data the it must be synchronous and meet all the setup and hold time volation. so i wnated to view it in chipscope. but i am unable use this clock internal signal while i am inserting for "chipscope pro inserter" for clock port and i wnated to see the datain (its also the internal signal form the differntial signal) whether it is meeting the constraints. how can i specify them in the chipscope inserter.

what kind of signal i should make as trigg ports. thanks

regard srik

Reply to
ekavirsrikanth

To check incoming clock at lower freq. rate, the best way would be to bring it out on a FPGA I/O pin and probe it with a scope (assuming you have some test pins available). Otherwise, if you have access to the differential clock traces on the board, then probe the differential input clock. Scope would show if you have a clean clock with low jitter.

-Vikram

Reply to
vikram.pasham

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