Metastability pipeline causes bad juju

Certainly you have shown that you *can* get by without simulation, but I find it hard to believe that this is more efficient than simulating. In simulation you can simulate any or all of a design (you could have tested your design in blocks) and access *any* signal in the simulation. Plus a simulation can make it clear whether a problem is logic or speed related. Of course a static timing analysis would identify any speed issues, but you can simulate without timing before even doing a place and route.

But to each his own... :)

Johan, Yeah, I did a very similar project to you, lots of cascaded DSP blocks. My DSP blocks were homespun, so I did initially functionally simulate them separately, but not especially thoroughly, while my hardware was being built. When the hardware turned up, I mostly used Chipscope to fault find. Your point about using a real input source for the blocks is a key advantage of Chipscope, especially in computationally intense apps like DSP. Chipscope revealed several 'design opportunities' when I tested with real signals, that simulation missed because of the limited time and effort available to make test vectors. Chipscope is also a winner for soft processors. It's easy to use Data2mem to upload new code to a BRAM, and debug your code in Chipscope without needing a P&R cycle. Cheers, Syms.

Actually, no I didn't. I used ChipScope and a real input source to the system. Since the filter blocks are from CoreGen, as well as the CORDIC, I wouldn't get more information about the internal signals from a simulation as I get from ChipScope.

Cheers

Good to hear that I'm not the only one using that type of design methodology... =)

Keep on Chipscoping in the free world...

johan