Why warnings: "Input <xyz> never used???"

Chris,

I didn't have time to look at your code. I'll just offer a couple of pointers here.

The Xilinx tools will optimize away logic you are not using. In doing so, a path that you thought was complete might endup without logic to connect to. A warning will be issued to let you know.

In general terms, take a look at your design and make sure that every single signal contributes to physical chip outputs. That's the key. If a singnal, say, the high bit of a counter, doesn't influence an output at all, the tools will remove that flip-flop and anything else prior to that flip-flop that does not add anything to the mix.

I soft of doesn't make sense in the context of building out a design, when you might not have all the blocks ready. It can be a real pain. One approach is to put in dummy blocks that do something with signals you are not using yet (a large AND function, for example, with the single output assigned to a pin).

Yeah, I gather what's happening is that it sees a constant applied to the input of some function, and reduces the logic. In the process, the input becomes superfluous.

Thanks for the reply.

Good day!

Hi Chris,

It's off topic, and it is probably none of my business to suggest (I almost used the word "criticize," but I instead used "suggest," so that you won't feel offended.), but why instantiate a vendor specific library primitive and Verilog gate primitives when you don't have to? These are the two examples I am talking about. ______________________________________________________________________ FDC FF1 ( .Q(Out), .C(Trig_in), .CLR(CompMatchOut), .D(h) );

______________________________________________________________________

Why instantiate an FDC? You should be able to replace it with the following code (Assuming that what I am doing is correct), and the synthesis tool should infer you an FDC.

______________________________________________________________________ reg Out;

always @ (posedge Trig_in or posedge CompMatchOut) begin

if (CompMatchOut == 1'b1) begin Out

Well, it was kinda fun ;-) I am also learning digital logic design by gradual experience, having never taking a formal course in it. So I asked myself "how does one determine the equality of two binary words?" I proceeded to twiddle with bits and bytes and truth tables on paper, and came up with the above blob of gates. I proceeded to implement it structurally, again just to cement my comfortability with this inefficient coding style.

Then I discovered on further perusing the Xilinx library that they had the same thing available to me already.

In the interest of learning I also experimented with the following way in dataflow style:

assign Q = & ( A ~^ B );

which seemed to work fine. I also wondered if it was possible to write the operation in the way you show here:

But actually, I wonder if you can do this:

assign Q = (A == B); // ???

Ok, thanks for the reply.

Good day!

Is the book you are using called Verilog Digital System Design by Zainalabedin Navabi? It sounds like that because that book gets into boring stuff like structural modeling.

Right, you probably should avoid using vendor specific features if there is no benefit like performance gain or logic resources reduction. Otherwise, keeping the logic generic makes sense for portability reasons.

I am personally sure how to answer this question, but even if you are interested in modeling a FF, in Verilog "reg" is as simple as things get. That being said, if you are interested in instantiating a vendor specific primitive like FDC from Xilinx's primitive library (Other firms have a similar primitive with similar names.), you can do that, but, of course, the code will become vendor specific.

Because of synthesis tools, I haven't used truth tables for years (Last time I did so in a college digital logic course.), however, when I had to build timing critical logic, I ended up reverting back to drawing gates on a paper (Really, equivalent of doing schematics.), mapping those gates into 4-input LUTs (Look-Up Tables), convert the paper schematics into Verilog assign statement equations using & (AND), | (OR), ^ (XOR), and ~ (NOT), and finally, slapping "keep" attribute of a synthesis tool (XST in my case.) to the wires coming out of assign statements to prevent the synthesis tool from messing up the carefully crafted equations I wrote (Still, XST ignored the keep attribute in some cases, but 95% of the equations survived intact.). What I just described is a really low level coding style, and I wish I didn't have to do so, but I had no choice.

Yes, the above "assign Q = (A == B);" should work, however, I usually like to specify the bit range, so that nothing unexpected happens. Generally speaking, Verilog is not a strict language, and lets to do things like comparison without specifying the bit range, however, I heard (I am not 100% sure.) that VHDL may not let you do that.

Kevin Brace

Bhasker, "A verilog HDL Primer." I also have the synthesis book, which I'll read after the primer.

I figured I'd be safe doing some real-world projects using structural modeling, since there isn't much to think about in terms of synthesis issues at this level.

So there's another book that deals with boring structural modeling!

I see.

Thanks for the input.

Good day!