BRAM timing problem


I am using a C to RTL generator that creates memories (VHDL) that result in inferred Block RAMS. During PAR, I get hold time violations. There seems to be an implicit 0ns hold time on the data out of the BRAM. However, the output of the BRAM goes to a latch and the enable on the latch is a function of my clock and an enable in the generated code. So, the latch enable is considered a clock, but appears to be a large skew between it and my real clock. The Xilinx timing wizard suggests making sure the two clocks use the same type of routing resources.

From what I have seen on the Xilinx site, the generated code follows

the standard approach to creating a memory (and inferring a BRAM); address is latched on the clock edge, data out is in an assignment statement.

Are the timing problems I see typical? If so, how do I deal with it? Or, do I need a different memory description where the data out is explicitly a function of the input clock edge?

thanks for your advice!

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"John" schrieb im Newsbeitrag news:

Uhhhhh, no good. Forget about messing around with gated clocks and latches. Use clock enable signals and FlipFlops (edge triggered latches). Do it in a clean way. Latches and gated clocks are not the choice of the day in FPGAs.

Regards Falk

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Falk Brunner

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