I'm using an FPGA (a Xilinx Spartan 3 XC3S400-4PQ208) in a design where one of it's functions is to sit between a cpu's SDRAM controller address and control lines and the sdram chips in order to register and buffer the signals and generate some additional chip selects. The data lines are not buffered. The processor in question (an Analog Devices ADSP-BF532) has the ability to pipeline the SDRAM address and control signals to support the delay introduced by this sort of buffering by one cycle.
address, control, clock signals (A0-12, DQMB0-1, RAS#, CAS#, clk, etc.): CPU FPGA SDRAM
data signals (D0-D15): CPU SDRAM
The question is how to analyze how long the FPGA needs to register the address and control lines on the input pins at the first rising edge of the clock signal received from the processor and then be able to have the buffered address and control lines available on the output pins on the FPGA at next rising edge of the clock. I'm not sure what I should be looking at in the timing analyzer to get the best estimate of what the timing parameters involved are. Also, what constraints should I set to minimize the timing overhead?
Thanks
Ed