IOBDELAY and DCM

Once your design is placed & routed, you can get a timing report that gives you the setup and hold requirements of each input to the clock pin(s). You can then adjust the clock timing if necessary using the fixed or variable delay of the DCM (Fixed is easier if you can find a value that works). By the way, if you make the timing adjustment with the DCM, you may find it easier to remove the IOBDELAY as it will give you a larger setup / hold window to center the clock in. Also note that the clock to output timing when measured from the clock input pin and not the internal global net can be quite long, so meeting hold time may not be as much problem as you might think from reading the IOB timing numbers in the data sheet.

HTH, Gabor

RobertP. wrote:

Why clock to output would be longer than specified in the datasheet (TICKOFDCM - pin-to-pin clock to output)? Also there is no Min TICKOFDCM specified - I found some info about how to estimate it (25% of worst case, but some people think it is not conservative enough).

I have the same gripe, with Xilinx. They expect you to use a tool, rather than the datasheet, to predict if your design will work. This makes it very difficult for people like you and me.

I was under the impression, also, that the min clock-to-out was 25% of the max time. I was later told that it's the inverse -- that the min clock-to-out is 75% of the max.

It's my opinion that Xilinx should include worst-case numbers, for all I/O standards, in the datasheet along with a note that says something like "It's possible that the timing may be better than what is printed in the datasheet. For most accurate results please use one of our timing analyzer tools."

The squeaky wheel gets the grease, so I suggest you voice your concerns with Xilinx.

Bob

If the clock period is long enough and the board-level clock skew is not too large, an easy solution is to use opposite edge clocking (out on falling edge, in on rising edge) between the devices. However you handle the clocking, the static timing report will tell you the external setup and hold times relative to the clock input pad. These numbers account for everything inside the device, inlcuding IBUFs, IBUFGs, BUFGs, IOBDELAYs, DCMs, etc. Just route the thing and let the tools give you the timing numbers. Then you go back to the data sheet and see if you can figure out where the numbers came from (if you insist).

Rob