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Lattice and Mentor seminar info pieces...

Hi

some info from the Lattice roadshow seminar at Mentor

1) 0.9 and 0.65 !? products are coming... 2) new FPGA products to be exptected (when you are back from sommer vaccation..) that goes for new FPGA products (not low end), not just some new device/derivate of existing things 3) something new is coming to the PLD offering as well (same timeline as above?) 4) serdes 2.5G+ will be included in some of the new devices 5) Lattice has completly solved the NBTI (and other submicron) issues (as much as I understood it means all the V4 NBTI like issues, things why xilinx is not shipping V4 silicon with working MGTs and why Stratix IIGX is delayed) are solved 6) EC family pricing can meed the S3 pricing in all cases where xilinx is not dumping on the high volumes 7) ECP and XP prices are EC+10%

please dont take those above as some official announcements, its only the answers I got ;) and possible my interpretation what may not be entirely accurate

Antti PS there was lots of free stuff from Mentor, incl. free lunch and optical usb mouse

Reply to
Antti Lukats
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You mean 90nm and 65nm ?

No hints on pin counts and resource ? [A MAXII ~clone with RAM would be nice :) ]

Fujitsu are the ones who would do the solving, not Lattice, and I would suspect anyone's "completely solved" claim, until proven by time...

On the topic of news, ST have their second member roll out on this family :

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&
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With a claimed 'volume' price of ~$30, and the raw MIPS performance and resources, it has the potential to shake the FPGA tree.

Similar in concept to the uPSD, [uC.ADC.PLD.Memory] but monstered up with 300MHz ARM9, 600MHz Dual MAX DSP, 200MHZ FPGA, & OnChip DRAM, plus peripherals FPGA users can only dream about. They still call this a MicroController :)

Success will depend on the device errata, how solid the tools are, and their ability to ship - [as other FPGA vendors are finding...?]

-jg

Reply to
Jim Granville

yes

some

no, but I think they have also recognized that CSP and QFN packages are nice, but no info if/when products in CSP will be available

not sure, what it will be, but yes Lattice thinks as well that missing ram in MAX2 is a BIG MISTAKE, almost as big as having the RAM not initializeable in PA3 !

(as

xilinx

sure actually that what they meant, that F has solved the issues, eg whatever issues they think there are

is

the

:

WAU!! I want that starterkit NOW !!

1MS/S ADC!, real DAC and hei they even have POR detect on that chip, I would not have even dreamed of that in such monster, the small things are usually forgotten

Antti

Reply to
Antti Lukats

Correct me, if I'm wrong - I have in mind, that somebody just told me that ST wants to stop their FPGA-activities?

Jochen

Reply to
Jochen

ST had a number of parallel efforts - they have licensed FPGA cores, and also were pushing a open-source path as well. It is the open-source effort that has been 'redeployed', and the winner was a licensed/stable/proven design which is what is used in these GreenField chips. In these, the FPGA does not need to be cutting edge, just mainstream.

All the Ethernet/UARTS/HDLC/Timers/DSP/CPU/DRAM are hard coded, so the FPGA can be smaller, and covers all the IO/Datapump one may need.

See

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-jg

Reply to
Jim Granville

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