Hi, group
I generated a IPIC interface with the "Create and Import Peripheral Wizard" in EDK's XPS to acces BRAM on the PLB bus.
I chose the user logic Master Support mode. And then try to develop my own logic based on the generated files. I have made a small FSM to test a single read and write (at the bottom of the message is my VHDL-code) My states are: a state (PrepareWr_State and PrepareRd_State) to make sure all the addresses are correct a state (ReqWr_State and ReqRd_State) for the request =>
IP2Bus_MstWrReq and IP2Bus_MstRdReq a state (AckWr_State and AckRd_State) for the ack that the IPIF can read/write from/to my ip => IP2Bus_WrAck and IP2Bus_RdAck a state (OkWr_State and OkRd_State) so I know everything went well
But there must be something wrong because it doesn't work at all. When I want to write something, my FSM stays in the ReqWr_State, and when I want to
read something it also doesn't do what it should do (or atleast what I think it should do)
Can anyone help me please?
Mich
-- TRANSITION_STATE_LOGIC
STATE_TRANSITION_LOGIC: process (ACTUAL_STATE, pushR, pushL, pushU, pushD, Bus2IP_MstLastAck, Bus2IP_WrReq, Bus2IP_RdReq) variable counter_Rd : integer range 0 to 15; variable counter_Wr : integer range 0 to 15; begin
case ACTUAL_STATE is when idle =>
if (pushR = '0') then
-- pushR is active low NEXT_STATE