Hi
I am trying to implement a shared memory interface between PPC and FPGA fabric. I am using EDK to create a dual port RAM and connect it to a DSOCM controller. I have been able to write to BlockRAM from my application code. My question is that how do I connect the other port of the BRAM to my FPGA design? Should the HDL module be added as a core from the " import peripheral" utility? If so, then which bus should it connect to?
Thanks Amit
You will probably need to add a plb bus to your system. On that bus I would guess you'd need a plb BRAM if cntlr and your own IP. The if_cntlr would be hooked to that second port on the shared BRAM and your IP would need to be a PLB master. So somehow your "FPGA design" needs to become the PLB master, probably using the IP wizard. Good luck...
Joey
Amit,
All you have to do is to declare the pins related to the other port external. I am assuming that your top-level design is in ISE and your EDK susbsytem is an instantiation in the top-level design.
/Mikhail
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