Timing constraints with asynchronous clocks

I need help solving a timing problem. I have two clocks one a fast one and a slower one, fclk and sclk. I use two flip flops to synchronize slower clock sclk to fclk, however sclk is used to clock some other items within the module. Is there a way that I can tell the tool to limit the path length from

fclk FF -> synchronized sclk FF -> fclk FF

to only one clock cycle of fclk?

Reply to
M. Hamed
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Yes, there is a way.

If you're using Xilinx tools, for instance, you would use a FROM/TO constraint which you can specify as the fclk period explicitly or with nanoseconds. You should find the FROM/TO syntax and details in the constraints guide.

If you're using other tools, please specify which tools you're using so you can get specific help.

Reply to

Yes I'm using Xilinx tools. For this scenario, FF1(fclk) generates ssclk (sclk after synchronization), and ssclk clocks FF2(ssclk) the output of that is the data input for FF3(fclk) after some logic. I wonder if I can specify a path from FF1 to FF3 cause that's the actual path that I need to limit to one clock cycle, or do I have to provide

2 separate paths FF1 to FF2 and FF2 to FF3?

Thank you.

Reply to
M. Hamed

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