I need help solving a timing problem. I have two clocks one a fast one and a slower one, fclk and sclk. I use two flip flops to synchronize slower clock sclk to fclk, however sclk is used to clock some other items within the module. Is there a way that I can tell the tool to limit the path length from
fclk FF -> synchronized sclk FF -> fclk FF
to only one clock cycle of fclk?