Hi All,
Can anyone tell me the solution to solve the setup or Hold time violation when running the simulation?
When i was running the simulation of my design, the simulator shows some warnings, which related to the setup time violation in a flip-flop with respect to CLK. Does anyone have the solution for this problem? Thanks.
The simplest solution is to run your simulation at slower clock speed. But if you must run at the clock speed when there is a timing violation, you can change your coding style to be more synthesis friendly, or change your design that will accomplish the same goal without timing violation.
Hendra
Are these warnings related to external signals ? If yes, you can fix the setup/hold violations by managing the generation of signals in your test-bench. If they are internal DFF.Q to DFF.D violations on the same clock, for setups you just have to try harder to meet timing during synthesis/P&R and add pipelines, simplify logic etc. In this mode, it would be difficult to have hold violations in an FPGA as the clock tree is already generated and all flops have non-negative clk->Q delays.
Make sure your testbench is not toggling signals immediately beside your clock edges. Put suitable delays in between edges and toggles that mimic the actual behaviour of your hardware. If it is not for real hardware try using a 1/4 of a clock period or something...
Cheers,
Ken
Consider using a synchronous testbench.
-- Mike Treseler
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