Difficulty in routing sinita/sinitb in block RAMs...

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Hi, all:=20

In my 40MHz design, ISE failed to route a few wires in the end, with = complaints on=20 timing violations also.=20

In fpga_editor, I could observe only a chunk of sinita/sinitb are green = fly wires...When=20 I first core_gen-erated these block RAMs, I excluded sinita/sinitb...Why = so special=20 about all these sinita/sinitbs?=20

Best Regards,=20 Kelvin

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