=_NextPart_000_0041_01C46406.F52F0FA0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable
Hi, all:=20
In my 40MHz design, ISE failed to route a few wires in the end, with = complaints on=20 timing violations also.=20
In fpga_editor, I could observe only a chunk of sinita/sinitb are green = fly wires...When=20 I first core_gen-erated these block RAMs, I excluded sinita/sinitb...Why = so special=20 about all these sinita/sinitbs?=20
Best Regards,=20 Kelvin