Need help on UNISIM.Vcomponents.all

Apr 12, 2008 4 Replies
L

Hi,



I'm trying to port some code from Xilinx to Altera and I'm in a bit of a problem by not having UNISIM lib on Altera.



I use only a few components from the unisim lib so may not be a big effort to write a vhdl component for each one of them, providing I know the details what they do exactly.



Can someone help me with the details of the following components:



SRL16E MULT18x18 RAMB16_S18 RAMB16_S9 RAMB16_S4 RAMB16_S18_S18


Or maybe there is a clever way of doing this.



Help is appreciated. Thanks.



Luis C.


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A

This may be helpful:

formatting link

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V

In Verilog-2001:

module SRL16E #( parameter INIT=16'h0000 ) ( output Q, input A0, input A1, input A2, input A3, input CE, input CLK, input D );

reg [15:0] r;

assign Q = r[{A3, A2, A1, A0}];

initial r = INIT;

always @(posedge CLK) if (CE) r

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