Hi,
I'm trying to port some code from Xilinx to Altera and I'm in a bit of a problem by not having UNISIM lib on Altera.
I use only a few components from the unisim lib so may not be a big effort to write a vhdl component for each one of them, providing I know the details what they do exactly.
Can someone help me with the details of the following components:
SRL16E MULT18x18 RAMB16_S18 RAMB16_S9 RAMB16_S4 RAMB16_S18_S18
Or maybe there is a clever way of doing this.
Help is appreciated. Thanks.
Luis C.