Hi all,I have two problem of SystemVerilog Assertion. About propertyimplication and sequence.1. Is//--------property rule (a,b,c); @(posedge clk) a |-> b ##1 c;endproperty//--------equal to//--------sequence rule; @(posedge clk) (a&&b) ##1 c;endsequence//--------2. I was told implication can be same or next cycle. Is same cycleequal to "|->"? And is next cycle equal to "|=>"?Thanks a lot!Best regards,Davy

"|->" implicate and sequence in SVA?

Nov 11, 2006 3 Replies

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Davy 19 years ago

Hi all,

I have two problem of SystemVerilog Assertion. About property implication and sequence.

Is //-------- property rule (a,b,c); @(posedge clk) a |-> b ##1 c; endproperty //--------

equal to //-------- sequence rule; @(posedge clk) (a&&b) ##1 c; endsequence //--------

I was told implication can be same or next cycle. Is same cycle equal to "|->"? And is next cycle equal to "|=>"?

Thanks a lot!

Best regards, Davy

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Jonathan Bromley 19 years ago

No. See the recent thread "implication operators in sva" on comp.lang.verilog. Also, you have parameterised the property but not the sequence.

Yes. See my post in the thread I just mentioned.

Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.

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Davy 19 years ago

Hi Jonathan,

Thanks a lot! Now I understand what's "vacuous success" :)

Best regards, Davy

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Shenli 19 years ago

To myself.

##1 is equivalent to @ (posedge clk). So ##N is equvalent to repeat (N) @ (posedge clk) ?

Thanks! Davy

Davy wrote:

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