sequence detection using shift register approach

Hi, I want to design a sequence detector circuit, there are two approaches .

The first approach is the traditional state m/c approach

The second is shift register approach for ex: for detecting sequence "10101011" i put a simple 8 bit shift register and look for the pattern "10101011" .I check the shft register value in each cycle whenever the shift register value is "10101011" the output is set to "1".

Which method is better the traditional state m/c approach or the shift register approach for sequence detection.

Regards, Praveen

Reply to
praveen.kantharajapura
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You'll need to define "better" in this case. If you need to run faster, the state machine may do better because it only handles one bit at a time. If you need to change the pattern you're detecting, the shift register and comparator will make life much easier. Also the shift register approach gets slower and bigger as the size of your pattern increases. Either approach can be optimised for a fixed pattern (the comparator turns into an AND gate for the fixed case). The state machine can be further optimised if the pattern is "regular" (symmetric or repeating). I guess the answer is "it depends..."

Reply to
Gabor

I am running at 150 MHZ is it really feasible to implement in shift registers. I have to look for 3 bytes( 24 bits).

Reply to
praveen.kantharajapura

HI,

In some fpgas it will be hard getting 5 levels (log2(24) as worstcase compare tree) of logic at 150 Mhz without pipelining. But I see no general problem.

Reply to
usenet_10

Hi Praveen, If so, in FPGAs you can often use the carry chain for this kind of thing. In UG002 (

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) go to the section "Implementing Sum of Products (SOP) Logic". 150MHz is a piece of cake, for a fixed pattern circuit you get 4 bits per LUT, 24 bits is only 6 LUTs and only 3 carry delays (the carry logic does two bits at a time). The biggest delays are getting on and off the chain. If you're looking for a programmable pattern, the same idea works, but you only get two bits per LUT. Two from your shift register, two from the programmable pattern. The LUT output is on when they match. Almost as fast as above, because the main delays are getting on and off the chain. HTH, Syms.

Reply to
Symon

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