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how to speed up my accumulator ??

I think he is saying that you should expect the maximum deviations to be n/m * Fref and n+1/m * Fref where n/m is the closest integer ratio that gives you an exact frequency that the NCO can make without jitter.

Example: Fref is 1 MHz, Fout is 211 kHz, 32 bit accumulator. This gives a step size of Fout/Fref * 2^32 = 906,238,099.456 ~= 906,238,099. This will roll over the MSB on 4 or 5 clock pulses. So your Fout will be composed of pulses of 4 clocks and pulses of 5 clocks with high and low times of 2 and 3 clocks. The corresponding jitter will be... geeze, this is hard isn't it?

I think you will get Fref/6 and Fref/2 as the range of jitter. I think the formula should be...

Fmax = floor(Fref/(2*Fout)) * 0.5 Fmin = ceiling(Fref/(2*Fout)) * 0.5 Fjitter = Fmax-Fmin

I expect you will see main peaks in your FFT at Fmax and Fmin, no?

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Rick "rickman" Collins

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Arius - A Signal Processing Solutions Company
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Reply to
rickman
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"rickman" schrieb im Newsbeitrag news: snipped-for-privacy@yahoo.com...

If someone really want to break this down to the last bit, I got a PHD paper here that is all about DDS, spectrum etc. But its german, 3 Mb pdf. If someone is intereted, drop me a mail.

Regards Falk

Reply to
Falk Brunner

Reply to
rickman

Hi Rick SLL will work for numeric_std.unsigned or bit vector:

formatting link

Thanks for the code example. Nice demo of area vs. speed at the hdl level.

-- Mike Treseler

Reply to
mike_treseler

Hi Rickman, Lots of thanks for the explanation and the numeric example. I will defently use it and afterwards I will probably measure the actual jitter frequency and compare it to the calculated results - when I'll get the results I will post them (for those intersted).. Thanks again, Moti.

Reply to
Moti

Hi Rickman, Lots of thanks for the explanation and the numeric example. I will defently use it and afterwards I will probably measure the actual jitter frequency and compare it to the calculated results - when I'll get the results I will post them (for those intersted).. Thanks again, Moti.

Reply to
Moti

Hi Falk, My german is pretty "rusty" :) so if the document is in .pdf format it will very hard... but if it's in a html format it can translated by google and then it will be possible to read it! Regards, Moti.

Reply to
Moti

It's involved... With your example of 211kHz from a 1MHz reference, the ratio of

906,238,099/2^32 has closest fractions in order of worst to best of

1/5

4/19 23/109 211/1000 1987386/9418891 19873649/94187910 57633561/273144839

The offsets are the ideal frequency compared to the ratio frequency:

211 kHz - 200 kHz 211 kHz - 210.52632 kHz 211 kHz - 211.00917 kHz 211 kHz - 211 kHz... Here Excel starts to lose digits:

The difference between 906,238,099/2^32 and 906,238,099.456/2^32 is about

5.03e-10 at which point small amounts of jitter are lost. If the jitter at that tiny offset is large, you will experience phase jumps when that beat frequency is felt. There's no way to filter those with analog filters.

Your largest observed peaks in the spectrum will be at offsets of 11 kHz,

526 Hz, and 9.17 Hz. You should be able to see the 526 Hz modulating the 11kHz for spikes much smaller than the 11 kHz peak.

Reply to
John_H

Good example maths, but is the principle right ?

For the example of 211KHz from 1Mhz, you have 1us quantize, and so will be able to generate 4us, or 5us periods, giving 250KHz and 200KHz.

Over many cycles, the 'wobbling' between these two will average to

211KHz. The more cycles, the better the match to 211KHz.

Over a 6 cycle snapshot, you might see 5@200, 1@250, and Favge 208.33Khz That's appx one part in 77 too slow. This 6 cycle frame has a freq of 34.6KHz

Next frame group would be (eg) every 79 cycles, to see => 14 @ 250KHz, 65@ 200KHz => 210.76923Khz, Error is now one part in 1000, and this finer frame is 2.65KHz ( etc ) as over wider frame snap-shots, the average frequency gets closer to the 211KHz ideal.

So I'd expect to see, on a spectrum analyser, 200KHz, (Dominant) 250KHz and 34.6KHz and 2.65KHz (etc) energies.

-jg

Reply to
Jim Granville

Did you actually plug it in to a spectrum analyser and see those tones?

Ten highest spurious tones:

55.000kHz -11.4dBc 367.000kHz -16.7dBc 101.000kHz -17.0dBc 165.000kHz -22.4dBc 9.000kHz -22.9dBc 257.000kHz -24.1dBc 321.000kHz -25.1dBc 147.000kHz -25.8dBc 119.000kHz -27.4dBc 37.000kHz -27.7dBc

Regards, Allan

Reply to
Allan Herriman

No, it was just 'back of an envelope' stuff, to get a feel for what repetition frames are likely, and so what the likely energies are.

Are these rounded to the nearest KHz, as I can't derive 55.00KHz either... a 19 cycle @ 1MHz frame, would be 52.63KHz ? It also seems strange to not see 200KHz, 250KHz... ?

-jg

Reply to
Jim Granville

Nearest 1 Hz.

Not strange at all. Switching between 4us and 5us periods does not mean you will see high level 200kHz and 250kHz components in the output.

As you said: "Good example maths, but is the principle right ?"

(This is getting OT for c.a.f. Suggest moving this to news:comp.dsp if you want to discuss the spectrum.)

Regards, Allan

Reply to
Allan Herriman

You should be able to copy and paste the text from a PDF into a web page for translation. But my experience has been that web page translations give you English that is not much easier to understand than the language you are translating from.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX
Reply to
rickman

We started with a 1 MHz clock. Right. The above recipe repeats after

14*5 + 65*4 cycles. That's a total of 381 uSec, or 2.624671 KHz.

How do I get 200 KHz or 250 KHz from that? What harmonic?

200 / 2.624671 => 76.200026 250 / 2.624671 => 95.250033

Those aren't close enough to integers for rounding to explain the differences. (I might have fatfingered something.)

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Reply to
Hal Murray

"John_H" schrieb im Newsbeitrag news:yB5td.10$ snipped-for-privacy@news-west.eli.net...

about

at

I guess the trick is noise shaping. Adding a (pseudo)random phase error to distribute the jitter energy over a wider band and also move it to higher frequencies. Sigma-Delta Style.

Regards Falk

Reply to
Falk Brunner

beat

Noise shaping is the right way to go for a superb quality synthesizer, but the correction phase error - the output from the noise shaper - needs to be applied based on the synchronous edge position relative to the "ideal" edge position - the input to the noise shaper. (Pseudo)Random doesn't do it.

All this assumes, of course, that there's an analog PLL driven by the single bit, noise-shaped NCO output. Without the PLL to filter out the high frequency phase noise of a Sigma-Delta style NCO, the jitter is still around

1 reference clock period peak-to-peak, maybe worse.

(NCOs are used by many folks in the comp.arch.fpga newsgroup who have no reason to visit comp.dsp.)

Reply to
John_H

Sorry, The frequencies are right, but I messed up the amplitudes. I realised the mistake when I checked by FFT-ing the output of a phase accumulator (using Excel!).

This is closer to reality:

367.000kHz -9.5dBc 55.000kHz -14.0dBc 477.000kHz -16.9dBc 101.000kHz -19.1dBc 321.000kHz -20.8dBc 257.000kHz -22.3dBc 165.000kHz -23.5dBc 413.000kHz -24.6dBc 9.000kHz -25.6dBc

etc.

I've only considered the spurious tones between 0Hz and 500kHz. Each of these tones will have an alias between 1MHz and 500kHz.

Note that the relative amplitudes of the highest spurious tones follow a 1/3, 1/5, 1/7, 1/9 ... sequence.

Regards, Allan

Reply to
Allan Herriman

"John_H" schrieb im Newsbeitrag news:S9std.14$ snipped-for-privacy@news-west.eli.net...

single

around

Yes.

???? Dont get it.

Regards Falk

Reply to
Falk Brunner

That answers a question I have had for a long time. It occured to me a long time ago to use an analog PLL to smooth out the ragged edges in an NCO clock. But no one I spoke to about it could say if it would work. I always figured that the low pass filter would do the smoothing for me.

I should never have doubted myself. ;)

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX
Reply to
rickman

I must be a 'no one'.

Rick, we have discussed this before, e.g. in this thread:

formatting link

This is something I've done in real designs. I've also developed tools for estimating the output jitter of the NCO, taking the loop bandwidth (and order) of the PLL into account. It is possible to achieve very low levels of jitter at the PLL output, if the frequencies are carefully chosen such that the higher level spurious signals at the output of the NCO are well outside the PLL loop bandwidth.

Exactly. Although this does require the phase detector to be linear (otherwise the jitter signals will be demodulated). Common phase detector types (e.g. most digital phase detectors driving charge pumps) aren't particularly linear due to inexact balance between the pull-up and pull-down current sources. A figure of 10% is sometimes quoted.

Regards, Allan

Reply to
Allan Herriman

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