internal tristates and busses

I'm not certain about the Xilinx parts, but in many FPGA's there is no tri-state capability in internal logic (onl;y in the IO blocks). So, whilst the synthesis should make your idea work, it will in truth create something similar to the MUX

designed

vector

design a bus(mux) to use internal tristate (TBUFs') can reduce the logic by significant amount, but for the new(current) technologies (S3/V4) TBUFs are no longer available so you end up using logic resources resources if targetting new families.

for S2/E there internal tristate (TBUF) based mux saves logic

antti

It is a good way when you have tristates and I have used it many times. However not many people used this technique and Xilinx have reduced and totally phased out internal tristates in their later families for this reason and others. For Spartan-II though it is a very good way to save CLB resources but don't expect the same results for Spartan-3 etc.

John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board.

designed

vector

lines,

appreciated.

Tip: if you can arrange that units sourcing the bus drive 0's when "tristated", either by using flip-flop outputs (use the built-in synchronous reset functionality) or using logic that can be finagled to output 0, then you can simply 'or' these sources together. This can be cheaper in gates or levels of logic than using a general purpose n-bit m-source multiplexer.

Ex-100%-of-TBUFs-user, Jan Gray

This is similar to what I do for wide muxes. But I don't bother with the tristate.

I use decoded signals like you have above, sel(n). They are both easier to create and use (in terms of logic). I then AND each bus with its enable and OR together the result. If you want to "help" the software optimally map this to LUTs, you can use two data inputs to a LUT along with the two enables. Then four of these LUTs can be combined in one LUT to give an 8 input mux in five LUTs.

The most Xilinx parts will give you an 8 input mux using 4 LUTs and some give a 16 input mux using 8 LUTs since they include the muxes to combine LUTs. Otherwise my approach above is the best I have found that is (relatively) technology independant.

This works better than the tristate logic which some parts (Xilinx) have. You can use the verilog wired-or type to avoid a lot of typing:

// register file

wor [15:0] read_bus; // 16 N-input OR gates.

bus_register #(.ADDRESS(0)) control ( .read_data (read_bus), ... );

bus_register #(.ADDRESS(1)) status ( .read_data (read_bus), ... );

Thanks for the tips, and hints. Very useful indeed.

Jason

designed

vector

lines,

appreciated.