Max7000s: how to use the enable of the dffe flip-flop?

Question

Dear all,I would like to register an address bus with the rising edge of theclk and if the LOAD is '1'. Below is my VHDL code.The problem is that when I analyse and elaborate with QII and see theRTL view I see a mux that choose A_I or A_O with LOAD and the theoutput of this mux goes to a dffe flip-flops (the output of thisflip-flops are feedback to the input of the mux). I would like to usethe enable input of the dffe flip-flops instead of the mux with theLOAD. How to do this? is the RTL view related with what finally willbe placed and routed?.Thanks a lot and best regards,Javientity DIR_LATCH is    port(  A_O:   out std_logic_vector ( 18 downto 2 );           LOAD:   in  std_logic;           CLK_I:   in  std_logic;           A_I:    in  std_logic_vector ( 18 downto 2)        );		end entity DIR_LATCH;--------------------------------------------------------------------------------- Definicion de la Arquitectura-------------------------------------------------------------------------------architecture DIR_LATCH_A1 of DIR_LATCH isbegin  -----------------------------------------------------------------------------  -- Definicion de la Arquitectura  -----------------------------------------------------------------------------  ADR_REG: process ( CLK_I )  begin    if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O( 2)

Marc Randolph · Accepted Answer

Oh my that's alot of typing (and very prone to typos). I believe the problem is that you have more than one controlling if statement within the process (in this case, more than one rising edge statement). But the reality of the matter is that you only need one!

ADR_REG: process ( CLK_I ) begin

if( rising_edge(CLK_I) ) then if( LOAD = '1' ) A_O( 2)

javid · Answer

Thanks a lot for the comments Marc,But my main question is that when I look at the RTL View of the vhdlfile I see that uses a D flip-flops and feedbacks the outputs of theseto the input of a mux that select with LOAD if the input to theDflip-flops are the previous output (A_O) or the present input (V_I).I will use the Altera CPLD Max7000s that seems to have a D flip-flopwith enable input and I would like that the LOAD input would go to theEnable input of the flip-flops instead of the feedback + mux solutionand leaving unconnected the enable input of the flip-flop. How to dothis?Thanks a lot and best regards,Javi------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Marc Randolph · Answer

Howdy Javi,Unless there is a very severe bug in the synthesis tools that you are using, you do this by using one (and _only one_) "if rising_edge(clk)" statement per process.  See below for examples.    Marc----------------------------------------------------------------------------------------------------------------------------------------------------------

Luc Braeckman · Answer

Javi,You haven't defined your FF completely.That's probably why you have a mux.You should have done something likeprocess (clk, reset)begin	if reset = '1' then		data  '0');	elsif clk'event and clk = '1' then		if load = '1' then			data(18 downto 2) Thanks a lot for the comments Marc,------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Symon · Answer

Hey Javid,Using Synplify? Look up syn_direct_enable in the manual.Cheers, Syms.

Max7000s: how to use the enable of the dffe flip-flop?

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