Hi all, is it legal to connect two INOUT ports in VHDL? If legal then what precautions we have to take to ensure proper operation (ex. some control signal to specify i/p or o/p)? Thanx
Hi all, is it legal to connect two INOUT ports in VHDL? If legal then what precautions we have to take to ensure proper operation (ex. some control signal to specify i/p or o/p)? Thanx
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