I have designed a slave OPB peripheral, simulated with VCS to check for the correct functionality and imported it into EDK. All was fine.
In EDK, when generating the netlist, the HDL code is synthesized using XST (Xilinx Synthesis Tool), so that the netlist can be generated.
The problem I'm having is that there is an "inout" port in my user logic that should go/come all the way up to/from the top level but for some reason, when XST generates an HDL wrapper to my user logic, it expects my sub-module to have 1 input and 2 output ports (see the error below) instead of just the one inout port, as if I had to use directly the input/outputs of an IOBUF instead of just one inout, e.g.:
// this is just an example: IOBUF txrx ( .I ( TXRX_IO_I ), // input .IO ( TXRX_IO ), // inout .O ( TXRX_IO_O ), // output .T ( TXRX_IO_T ) // ouput enable );
In my code I have something like this:
// port declaration inout TXRX_IO;
assign TXRX_IO = TxEn? 1'bz:0; // output, pull up assumed
if (CanRead) Read_reg