VHDL inout used for non bidirectional uses

There is a way to do this, it is called mode "buffer". However, some synthesis tools don't handel it correctly. I typically just make a temporary signal.

In vhdl-200x, the next release of VHDL, we are making a "buffer" and "out" signal the same.

For some reason VHDL won't let you read a mode "out" pin, just one of VHDL's quirks I guess - Verilog doesn't seem to have this problem. And, no you don't want to change the pin to an inout because then you are reading the signal on the wrong side of the I/O buffer. Just use a buffer to connect the internally generated signal to the output pin. Then you can read the internally generated signal as much as you want, and the Xilinx optimizing software will throw the buffer out when it optimizes the design.

Dan

around

and

style?

VHDL's

In this case my situation is reversed. I have an out pin (it's the Write*/Read SRAM line) and want to read it internally (one use would be to control the tristate data outputs).

Brad Smallridge a écrit:

As has already been told, if you use an inout port you will read the pad signal, thus adding output and input delays. You can use a buffer port instead of inout although this is quite a pain, or use an internal signal that you assign to your port:

port ( ... sram_rw_b : out std_logic; -- the output port ... ); ... signal i_sram_rw_b : std_logic; -- the internal signal ... sram_rw_b

If I need to read an OUT port from the same process that drives it, then I have written a state machine that lacks a process variable or architecture signal to maintain the local state value.

For a simple entity example, a port output may be exactly the same as the local state value. In this case, declaring an extra variable or signal might seem annoying.

However, for an industrial-strength entity, this is seldom the case. Processes maintain lots of state values that are only needed locally.

For example, imagine a process that watches an single bit IN and drives single port bit OUT with a '1' when the input frequency is within a certain range or '0' otherwise.

-- Mike Treseler

There are analog/timing reasons for wanting to use a signal after it has gone out and back in the same pin.

I'd probably try to stuff that sort of hackery into a subroutine.