global clock (gclk) input at xilinx virtex4 fpga

Howdy Joe,

If the clock tree's within a device is designed correctly (most all of them are - haven't heard of any problems with V4), then one clock should work just fine on a device of any size - and is actually preferable since you only have one clock domain to deal with.

Have fun,

Marc

The multiple clock inputs are for when you need to support a board design that has multiple clock domains, not for driving the same clock to the whole FPGA.

I would expect that using multiple clock inputs for the "same" clock would just give you multiple clock domains within the device, with all the attendant trials and tribulations of synchronizing between them, only for no reason.