difference of variable and signal

thx, Jim, Sorry, the examples are miss leading. My main concern is the different during design flow. Let me restate my question, During HDL synthesis, that's the difference between them? Will that make any different after synthesis(place & route)?

variable: store information in a memory cell signal: "wire" to send information to other modules if the information in signal is needed later on, a latch is put in the signal line

"YiQi" schrieb im Newsbeitrag news: snipped-for-privacy@g10g2000cwb.googlegroups.com...

Falk Salewski schrieb:

I doubt it. There are plenty of signals in every HDL design without any latch. As someone pointed out before, it's a complicated story (and so answer) of HDL principles.

Regards Falk

Thanks both Falk, In a FPGA, does a latch and a memory cell make any different? Isn't it the same ?

In most FPGAs there are no latches. You should avoid inferring latches in these FPGAs, because they are created out of logic gates.

Black-RAM in FPGAs can often be accessed using the edge of a signal. -> No Latches.

For standard cells you may use latches to get a compatible behavior to standard DRAM.

DRAM is one capacitor and one transistor. Latches are closed loops build out of logic gates.

Ralf