how to change cclk frequency ?

wolflame schrieb:

the clock rate to higher rate in ISE when generating PROM file, but it always start as 2M clock..

you cant change the initial CCLK rate, its always default, only when special command sequence is shifted in the CCLK clock frequency changes to its programmed value

Antti

set the clock rate to higher rate in ISE when generating PROM file, but it always start as 2M clock..you cant change the initial CCLK rate, its always default, only when

and not only that, if you wanted the FPGA to change CLk speed any earlier ( ie before the bitstream loads ) it would need to be clairvoyant ;)

-jg

Jim Granville a écrit :

Now *that* would be a real technology breakthrough !

Nicolas

the clock rate to higher rate in ISE when generating PROM file, but it always start as 2M clock..

If you need to program the part at the maximum allowable rate, your best bet is to use slave-serial mode and generate the clock with a more accurate oscillator. Usually the maximum rate of programming will be limited by the PROM, not the FPGA. The clock rates listed in the configuration settings are approximate, and you need to take into account the maximum rate when selecting the frequency for a particular PROM. If the short portion of the configuration which takes place at 2MHz makes a difference to your application, it seems you are trying to push the master-serial beyond its useful range.

just my 2 cents, Gabor