We have a board with 2 Virtex II 6000 devices. They are programmed from independent bank of serial eeproms in Master serial mode.
One of the FPGA's (slave fpga) is not being programmed consistently. On power up it sometimes programs and at times fails. If after powerup we manually start a programming cycle by pulling program pin low, it programs properly. Observed INIT pin going low before DONE goes high on slave FPGA, indicating CRC error.
Also observed that slave FPGA initiates the program cycle earlier and has higher serial clock frequency than master.(using the lowest frequency 4 MHz)
Hooked up logic analyzer and counted the clock cycles in the programming cycle. The slave FPGA clock count varies, both when it fails and when it programs(manual program intiation). When it fails it is lower than the required count but varies from one try to another. When it succeeds it is higher than required and also vaires from one try to another.
Master FPGA clock count is always the same.
Any suggestions on what could be causing this problem?
Thanks Brijesh