Problem with Spartan 3 StarterKit

Hello, ich have the Spartan3 StarterKit from Digilent. When I start the programming process in impact, all LEDs on the board go red, and on the screen an progress dialog appears. When the progress is at about 98%, it stalls for 8 seconds, and then the message appears : "'1' : Programming terminated. DONE did not go high" Can you help me ?

Regards Thorsten

Reply to
Thorsten Kiefer
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More data please:

  • Which starter kit?
  • What file are you trying to load?
  • What are you trying to load it with?

Are you confident that the file you are trying to load is correct for the device you are trying to load? It may be that you're trying to load a file for the "next smaller" FPGA.

G.

Reply to
ghelbig

The one with the Xilinx XC3S200

eq2.bit (A 2 bit comparator. 4 switches are input, and 1 led is ouput.)

impact

i created the project for exactly that device

TK

Reply to
Thorsten Kiefer

Can you successfully load the example project, s3demo.bit?

If so, then there must some problem with your generated .bit file.

Reply to
Paul Urbanus

Is it shipped with WebPack ? I cannot find it in my ISE WebPack installation.

Reply to
Thorsten Kiefer

No, same message

Reply to
Thorsten Kiefer

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Thorsten Kiefer schrieb:

Reply to
Christian Schrader

OK I got it. The configuration mode jumpers were set to "master serial". I set them to "Jtag". But the program is not persistent. How can I make it persistent. The JTAG chain shows a second device : xcf02s. Is that the flash prom ?

Reply to
Thorsten Kiefer

You are correct - the memory in the FPGA is volatile (it's SRAM) and your program will vanish when power is removed.

Correct also on the second point - you must program the platform flash (xcf02s) with your fpga code. However, to do so you must first run the IMPACT tool to generate a programming file (I like to use the .mcs format).

*IMPORTANT* When you set the properties for generating your .bit file, make sure that you select the configuration clock as CCLK, as this is the clock that drives the xcf02s during configuration. There is no need to change this to JTAG clock while you are developing your code, as the IMPACT will recognize this mismatch and change the configuration clock from CCLK to JTAG whenever you load the .bit file directly into the FPGA.
Reply to
Paul Urbanus

Also, don't forget to change the configuration mode back to master serial after you have programmed the platform flash. Oh, you have to either cycle power or press the 'FGPA program' switch (if this is one on the board) before the FPGA will be loaded from the platform flash.

Reply to
Paul Urbanus

I got it working now. I can leave the jumpers in "master serial" while I program the flash. The fpga boots automatically from the flash.

Thanks for your help!

-Thorsten

Reply to
Thorsten Kiefer

Exactly that happens to me when I select "Verify" in the dialogue. Loading works when I don't check "Verify".

Vielleicht hilft's.

--
	mac the naïf
Reply to
Alex Colvin

Yes, the way I always do it is to just leave the jumpers set for master-serial mode and then just program the XCF04 prom every time.

And if you check the "Load FPGA" checkbox when downloading, the FPGA will automatically load from the prom at the end of the programming.

Cheers,

Anthony Burch Getting Started With Xilinx FPGAs Video Guide

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Reply to
Tony Burch

Yes, the jumper setting is PARTIAL solution, the JTAG is always enabled and it always OVERRIDES the other configuration modes, but...

Xilinx has never managed to the JTAG configuration with Impact work correctly and the result is that depending the configuration and impact version and cable version the jtag configuration may fail if the master serial configuration is enabled and the configuration memory containts a bitstream. If the config eeprom is erased then leaving the jumpers in master mode would not do any harm and you can use jtag config.

so you just trapped into a XILINXBUG

Antti

Reply to
Antti

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