Libero 7.2

Hi to everyone, i've started using Libero 7.2 and I found a very nice feature (let's say), when you import package files from your package directory, it just copy it to the hdl directory and use them. In case you want to change the package is useless changing it in the package directory because it will use the one that has been copied on the hdl directory. Is it reasonable??? Can anyone explain me the advantages that this "hidden" behaviour will lead to, either than making people crazy? Thanks a lot

Al

--
Alessandro Basili
CERN, PH/UGC
 Click to see the full signature
Reply to
alessandro basili
Loading thread data ...

alessandro basili schrieb:

things are not always reasonable. the libero/designer is just to make people crazy.

use it at the minimum, that is prepare all files using some other tools, then port to libero and try to get the bitstream file minimizing the work you do with libero.

Antti

Reply to
Antti

This is what I usually do, I use emacs to edit vhdl, synplify to synthesize it and Modelsim to simulate it and Designer to make the P&R and to generate the back-annotate vhdl for the post-layout simulation. Unfortunately I'm still not able to use them without the Libero setup, which configures all the libraries to compile and everything, but it makes you crazy. I thought about migrating on something smarter but still don't have other choices.

--
Alessandro Basili
CERN, PH/UGC
 Click to see the full signature
Reply to
Al

All the Libero tools can be used standalone. And this is what I do.

It looks like you are missing some setup information. Compare your paths with what you get from your Libero project directory, or post the error message you get.

Regards, Daniel Leu Inicore, Inc.

Reply to
Daniel Leu

I would recommend this order:

  1. emacs+vcom for entry and syntax check of uut and functional testbench code. define a vhdl-mode project for the source directory.
  2. Modelsim to debug uut and functional testbench code.
  3. Run synplify on the debugged uut source and fix synthesis errors.
  4. Run libero place+route on the synplify netlist and check static timing. A post-layout sim is not always needed for a synchronous design.

This keeps libero out of the loop until it is actually needed.

-- Mike Treseler

Reply to
Mike Treseler

Hey that's a great suggestion! Anyway to start Designer is not really needed Libero, you can even live without it. I had never had this approach, in the sense that I always checked syntax directly with the Synplify, moreover I always used the testbench just for the post-synthesis simulation, never for the functional, maybe this can help me quicker to find out "functional" problems. Thanks Mike

--
Alessandro Basili
CERN, PH/UGC
 Click to see the full signature
Reply to
Al

This is the default path laid out by the device vendors, but it seems backwards to me.

I expect that it will.

-- Mike Treseler

Reply to
Mike Treseler

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.