When configuring a virtex fpga with a prom in master serial mode, how is the clock generated by the fpga. I presume I don’t need to input any other clock other than my normal fast clock of 100MHz.
When configuring a virtex fpga with a prom in master serial mode, how is the clock generated by the fpga. I presume I don’t need to input any other clock other than my normal fast clock of 100MHz.
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