Several Problems with Spartan2 Configuration


I'm doing a work for my studies which consists who programming an FPGA (Spartan 2, xc2s200). We have three plattform with it:

-A BurchED Board

-Two selfmade PCB with all other components (RAM, PROM, Clock Generator, UART modul), one was soldered by the previous work, the other by me.

We want to boot the FPGA in Master Serial Mode. It works OK on the BurchED Board, so controlled the configuration pins on both boards, which are correct (M2, M1 too ground; M0 is not important in that case, but also to ground.) I actually never got the FPGA booting from Flash (xc18v02). I can program both flash.

The second problem is that I can't configure the board i soldered myself through JTAG. When I choose init cable in impact, the FPGA is correctly recogninanize as xc2s200, but when I choose programm, the programm says "incorrect idcode". I looked at it, sice are zeros at one in it, it can't be a stuck-at fault.

Useful infos: The pullups are down one the old board with 4.7 KOhm, on the newer with

5.6 kOhm (there weren't any 4.7 left)

Can anybody help me ? I have read the newsgroup and found no solution.

Reply to
Thierry Gschwind
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Hi Thierry,

difficult to say, what the problem could be, however it might be worthwhile to always check "" and simple type in

- as an example - "impact incorrect idcode" and read through the database hits. It should give you a hint or an idea howto look closer to your problem ...

Concerning JTAG programming I think you need to disable one or the other option - can't remember anymore - and the problem might disappear ...


Reply to
Markus Meng

The guys who designed the hardware hardwired M2 and M1 to ground, it's nearly not possible to change them.

I have read all on Xilinx Support, but nothing helped me. Also what I read if I understan it correct, JTAG has always priority over other programming.

Reply to
Thierry Gschwind

I believe that the only thing that messes up the JTAG is the PROG pin.



Reply to
Simon Peacock

We had similar problems in the past with Spartan2/Virtex. Although the datasheets state that JTAG has alway priority, configuration through JTAG with the mode pins set to any but JTAG-mode failed. I once read here in the news group that that's because of the dynamic reconfiguration feature of these chips. IIRC,you would have to issue some kind of start command through JTAG to make the configuration become valid. The problem with the boot from PROM not working reminds me of own experiences when the FPGA would not start up because the PROM file was build with the startup option "JTAG-CLK" instead of "CCLK". In that case the FPGA waited after loading the bitstream for some clock pulses to appear on the JTAG TCK-line which, of course, never came. If nothing helps, you could take a look to the configuration lines with a logic analyzer to see where the problem is. (Is /PROG low for some time followed by /Init going low, too? - FPGA starts booting. Does Init return to high some times later? - Configuration RAM cleared, data stream should be shifted in now. Is there a cclk signal? - FPGA is in master serial mode, indeed. Does /Init not go low again? - Configuration bitstream has no errors? Does DONE go high, finally?

- Boot was succesful.)

Regards, Jens

Reply to
Jens Hildebrandt


If you're using a QFP (which I presume you are if you've soldered this down yourself) it's not impossible to lift a pin, even with pin pitches of 0.5mm.

You'll need a stereo microscope or other good maginifer, and a scalpel with a new blade.

Prepare the area with pleanty of flux. Position the scalpel tip between the pin in question and one of its neighbours. Put pleanty of solder on the iron and heat the pin in question, gently levering against the neighbour. You should be able to prise it up, but be careful with it, don't bend it up and down too many times or it'll snap off.

Clean up the adjacent pins with solder-wick and re-do and than need tidied up.

You can then get a flying wire on the pin you've lifted, but be careful with it, as I said above it's not mechanically strong and you don't want to overheat it.

Not that I've ever had to do this of course ;-)


------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design Cyclone Based 'Easy PCI' proto board

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Reply to
Nial Stewart

I have a microscop. I had to resolder the whole side where there are M1, M2 and it's look quite ugly now, but I will retry.

Nial Stewart wrote:

Reply to
Thierry Gschwind

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