Hallo, I have made a clock divider (1 MHz) with a counter connected to system clock (50 MHz). This counter has a threshold which goes high on the last count. This pulse drives some blocks as a clock enable (the clock input of these blocks is connected to system clock). Every block is falling edge sensitive.
The pulse drives also a FSM where every state send high/low 4 signals.
In this way there is no gating clock, but now pulse signal has high load.
I can't use DCM because of the too low out frequency.
What could I do to reduce load and skew?
The only way is to add a BUFG?
Many Thanks in advance and sorry for my terrible english Marco Toschi
I assume that you'd be using a BUFG for your clock? You probably want to do that, if you aren't already.
Simplest way to do what you want (I think) is to replicate your clock enable signal (or use a bufg, I guess) - what synthesis tool are you using? Some of them, at least, do this automatically.
Why are you using the falling edge? Your 50MHz clock should come from a BUFG and only use one edge (either rising or falling) in all the places it goes. So, the counter and the 'blocks' you mention should all use the same edge. Is that what you are doing?
The enable signal will be automatically buffered by the Xilinx routing. As long as you've told the timing analyser that your main clock is going at
50MHz, you don't have to worry about 'load' (or fanout as it's often called) or skew. To send a 1MHz signal out of the FPGA, as you mentioned in your other thread, you might like to consider also generating a 2MHz enable from your 50 MHz counter, as well as the 1MHz one, to toggle the IOB flip-flop.
There are an ADC and a DAC connected to FPGA pins, and they are falling edge sensitive.
This morning I have verified that XST generates a fanout at least of 3 on the signal used as clock for FSM indipendentely from the number of signal to drive into FSM. So if the clock is the system clock buffered automatically by XST, the load and skew aren't a trouble and they aren't "visible".
Even if I reproduce the clock signal and the state machines, every clock signal has a load of 3. It takes a skew of 1ns and a delay of 2ns.
In my case I can't use the system clock. At this point I think the only way is to use a BUFG.
So I have placed a BUFG and the trouble seems to be solved, but the DAC reacts in different ways depending on the level of optimizazion of mapping and post-placing.
I send a clock signal of 1 MHz, a Chip Select, and 16 serial data bits.
I have thought that depending on the level of optimization, the delay between clock and chip select could be different, so the DAC don't go into power on state.
OK Marco, let me see if I understand your design. You have an FPGA. It has a
50 MHz clock available. Let's call this the 'masterclock'. Attached to the FPGA are a DAC and a ADC. These parts are designed to be clocked at 1MHz, let's call these the DAC_clock and the ADC_clock. Here's some VHDL.
--snippet to generate clock enables if res_n = '0' then --add async resets here elsif rising_edge(masterclock) then count >>
Sorry Marco, this last part of your post is a mystery to me. You only need one 'clock' signal, the masterclock. It should have a fanout of more than 3! The 1MHz enable signal should go to all the FFs in your FSM, I think this signal should have a lot more than 3 loads as well. A delay of 2ns and a skew of 1ns is fine for this clock. Do you want to post some code? Anyway, if this makes any sense to you, post back, and we can talk about the timing constraints you need to set! HTH, Syms.
My code is similar to that you posted, the idea is the same. The only difference is I have used core generator to create the components. I will try drawing a timing diagram.
Masterclock has a high fanout, about 100. I have replicated 2 times the clock pulse at 1MHz and the state machines to verify if it could low the fanout. I have obtained that every replicated clock (the pulse at 1 MHz) used to drive a state machine has a load equal to 3.
I have tried now avoiding replication hardware and BUFG connected to clock pulse. In this way clock pulse at 1MHz hs a load of 7. There are skew 1ns and delay
2,5ns. I have made lots of experiments because I thought the main trouble could come from that.
If I want update every channel, I should send 4 words of 16 bits and 4 ChipSelect. (I have made lots of post-place simulations and everything is ok).
I have sent them and not every channel is updated. Which channel depends on level of optimization.
If I try to update the out of only one channel (sending 500-1000 16-bit datas sequentially to DAC) the system works well.
It seems doesn't accept a sequential update of different channels. I'm sure to wait the time needed to update a single channel. I have verified it.
Could be a trouble depending on DAC and not from my logic?
In example the control unit which read what channel to update and configure the nultiplexer?
Many and many thanks for your precious answer Marco
Why do you want to lower the fanout? Have you connected the clock pulse at
1MHz to the clock input of any FFs? If you have, this is your mistake. It should only connect to the CE pins. The clock pins of *ALL* your FFs should connect to the 50MHz masterclock.
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