Webpack Vs. ISE

I have used Webpack 4.2 something and I believe the ISE foundation of about the same edition.

I have found that they are essentially identical, with the following differences:

Webpack does not have the core generator. You cannot use the block rams and other on chip resources.

I also am not sure that you can change the synthesis flow from XST to any thing else. I don't know this for fact, as I have not tried to do this.

HTH

Clyde

Dave wrote:

about the

and

That's not true Clyde, you've just got to know what they're called and instantiate them directly.

See the Picoblaze and 'VirtexII picoblaze (more instruction memory) on a SpartanII' projects on the Downloads page of my web site below.

Both done with web-pack and both instantiate blockrams.

Nial Stewart

------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design

Marc,

Xilinx has four versions of their ISE software. They are:

1) Webpack 2) BaseX 3) Foundation 4) Alliance

1 and 2 are subsets of Foundation which has the XST synthesis tool. The differentiator is that #3 has the full toolset with support for all Xilinx devices. Numbers 1 and 2 have XST but only support the low to mid range devices. Alliance is the third party flow which does not include XST. It should be noted that XST does not support devices based on the 4000 architecture. i.e. 4000 family, Spartan/Spartan XL. All other families are supported. If you need support for the 4000 stuff you need to go third party.

Hope this helps...

Matt

FPGAs.

XCESS

using

Foundation

to

need

appreciated.

Matt,

Thanks for the info. I looked at the Xilinx web site and what they are now calling Foundation is not what they had called Foundation previously. Previously, ISE started and Foundation ended with version

4.x (which used Aldec technology). What they are now calling Foundation is something completely different than what I was refering to. I stand corrected.

Marc

Matt wrote:

I just did a little experiment with the webpack software, instantiating a fifo in the block ram.... and the software black boxes it because it doesn't know how to hook it up.

The .edn file from the core generator is missing, and as such XST does not know how to configure the block ram.

This is consistent with information I received from the Xilinx Apps guy.

/\/\/\/

Sorry for my confusion on Webpack vs. Foundation.

Clyde

Nial Stewart wrote:

doesn't

not

What are you trying to instantiate? If it's a component that you previously generated from Coregen then it won't work as coregen stitches whatever Blockrams together to get the structure you need, creates a wrapper round them and gives it a sensible name.

If you try to instantiate the wrapper web-pack won't know what you're talking about.

Have a look at the data sheet for whatever device you're targeting to see what the blockrams should be called. As an example a 256* 8 bit dual port ram in SpartanIIE is RAMB4_S8_S8, you'll have to check the data sheet for port names.

If you want bigger/wider structures than you get with one block ram you've got to stitch them together yourself (with a wrapper if you want).

It would be almost a complete waste of time for Xilinx to release web-pack if you couldn't access blockrams.

Nial.

------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design

Then, please enlighten us as to how to use the block rams with Web-pack, without using the core generator.

I looked at your web page and did not see in your example projects how you did it.

Clyde

Nial Stewart wrote:

In comp.arch.fpga Clyde R. Shappee wrote: : Then, please enlighten us as to how to use the block rams with Web-pack, without : using the core generator.

: I looked at your web page and did not see in your example projects how you did : it.

Here is how I instantiate in in some verilog project:

RAMB4_S16_S16 ram0(.DOA(),.DOB(rdo_data_a),.ADDRA(rdo_wfifo_cnt),.ADDRB(rdo_rfifo_cnt), .CLKA(!mclk_i),.CLKB(rclk),.DIA(dba_r[15:0]),.DIB(16'b0), .ENA(1'b1),.ENB(1'b1), .RSTA(1'b0),.RSTB(1'b0),.WEA(rdo_read_rrrr),.WEB(1'b0)); RAMB4_S16_S16 ram1(.DOA(),.DOB(rdo_data_b),.ADDRA(rdo_wfifo_cnt),.ADDRB(rdo_rfifo_cnt), .CLKA(!mclk_i),.CLKB(rclk),.DIA(dbb_r[15:0]),.DIB(16'b0), .ENA(1'b1),.ENB(1'b1), .RSTA(1'b0),.RSTB(1'b0),.WEA(rdo_read_rrrr),.WEB(1'b0)); Hpe this helps.

Bye

--
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

I used Webpack version 5.x a while ago and was able to access block rams by infering them rather than instantiating them. I don't know if this worked in version 4.x. For this approach to work, you need to craft your Verilog code to match the BRAM structure so the synthesizer could see that you REALLY want BRAM and not distributed ram. It took me several iterations to find the proper Verilog style.

Here's code that seemed to infer BRAM for a Spartan chip:

// ____________________________________________________________ // IN Buffer reg [7:0] in_buf [511:0];

reg [8:0] in_rd_addr; always @(posedge clk) if (fifo_rd_valid) in_buf[in_ptr]

without

I already have.

"Have a look at the data sheet for whatever device you're targeting to see what the blockrams should be called. As an example a 256* 8 bit dual port ram in SpartanIIE is RAMB4_S8_S8, you'll have to check the data sheet for port names."

And see Uwe's example above/below.

Spoon feeding bit.....

If you look in webpack/vhld/src/unisims/unisim_VCOMP.vhd you'll see the models for all the rams supported. RAMB4 is supported in Spartan devices (as specified in the SpartanII-E data sheet), I presume RAMB16 configurations are supported in Virtex devices.

did

Download pico2spart.zip, unzip it and look at ../SW/picocode.vhd

This contains five blockram instantiations with the associated configurations containing the software for the Virtex picoblaze in a SpartanII.

These Blockrams are 1024 addresses* 4 bits.

For an example of a singla 256*16 ram download picoblaze.zip, then look at ../sw/ROM_form.vhd . This is a template file, but it's exactly the way the ram's instantiated in a real design.

Did you ask the Xilinx apps guy "Does web-pack support blockrams?", or "Does web-pack support this ram I've generated with Coregen?" ?.

As I said, it would be almost a complete waste of time for Xilinx to release web-pack if you couldn't get at the Rams.

Nial.

------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design