FPGA quiz: what can be wrong

YES

I d* No problem in VHDL, constraints, and all other FPGA files

• No problem in configuration
• No problem in PCB, power supply, connections, wiring.

When you say the VHDL file is "correct", to what specification does it conform? You haven't said what you *expect* or *require* the VHDL to do. It looks like it should output some_signal to LED1 and blink_one_second to LED2 - but this isn't the case when the FPGA is configured.

What happens if you remove the blink_one_second signal completely? Does LED1 still blink?

Somehow the compiler/optimizer thinks 'some_signal' will never reach '1'? If e.g. both signals route through the same LUT the 'both blinking' is a don't care as far as the compiler is concerned.

-- Bas

its nothing related to compiler (or any FPGA implementation too) to think something wrong

Antti

the VHDL code driving LED when entered in schematic would be a single line going to LED2,

the signal driving LED2 could be disconnected from LED2 IOB or connected to some other IO or anything else, the LED1 would still have the same behaviour, it would blink in sync with the signal that was driving LED2 if some_signal is high, and be constant low if some_signal is 0

Antti

What about having the boundary scan (JTAG) implementation shifting the value of the output connected to LED2 on the output connected to LED1 ;-)

Zitierten Text ausblenden -

NO that isnt the case either, the same behaviour would appear no matter to what IO pads the LED1, LED2 are locked

Antti

What are the I/O standards and VCCO used for the two pins?

Are they the same, or are they in different banks ?

If you optically isolate the two LED's so LED1 can't see LED2, does the problem go away ? ( i.e. one LED is almost but not quite biased on, incident light from the other LED pushes it over the edge)

Brian

Not the VHDL Not the UCF Not the synth. Not the P/R Not FPGA fabric Not the supply Not the PCB Not the Led Not the FPGA version Not the FPGA vendor Not the DCI Not the DCM Not the Ground Loop Not Coupling issue Not the LED itself ...

Maybe in Absolute Maximum Rating ? You are stocking your FPGA boards under -65 Celcius ;-) (storage temperature) just funny

---------------------- More serious: Junction temperature ?

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- Laurent

no temperature no environment issue

Antti

If you desolder LED2 from the board, would LED1 still blink in sync with the signal at the LED2 I/O pad when some_signal is low ?

Laurent Pinchart

wau, also good guesses!!

the io banking is not issue the io standard is ir-relevant also not the supply to different banks there is no opto coupling issue the same behaviour on pads could be observed with no connections (no LED)

Antti

read my posting again when some_signal is 0, then only LED2 blinks when some_signal is 1, then both LEDs blink

the actual connection of the LEDs has influence to the behaviour

Antti

ups sorry, my mistypo: should read: the actual connection of the LED's has _no_ influence on the signal behaviour. sorry

Antti

Please let us a VHDL example or a partial VHDL. Then we will p&r to our FPGAs Platform, and we will see !

--------------- You do not test all conditions in your VHDL -> then synth. uses some async D-latch?

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BUT THIS IS A STUDENT-ISSUE KIND -> NOT AN ANTTI-ISSUE

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- Laurent

Is one of the signals involved connected to a global tristate or powerdown pin on the FPGA ?

Brian

wau, keep getting nice suggestions! :) no power down or FPGA power management is not the issue

Antti

This doesn't obviously answer my question. You don't mention LED1 in your description of the schematic.

If you change the frequency of blink_one_second does the other LED change frequency with it?

Hi Laurent,

the VHDL code for signal LED2 is essentially a single wire point-to- point it would be single horizontal stright wire in scheamatic version.

========== cut here ==========

signal blink_one_second : std_logic;