I am working on an instrument that currently uses a 300 MHz TI dual- issue DSP + A/Ds + a micro. Under "normal" use, I can get a week out of the D-cell batteries the device uses.
At the moment, I am considering replacing the DSP and other glue with an FPGA, but I don't see many low-power options.
Any suggestions? Any low-power FPGA experiences to share?
I asked an Altera FAE and he very rudely answered "Low-power Altera FPGAs aren't on the road map"...yeah and I bet low-power CPLDs (ala MaxII) weren't on the road map until CoolRunner started hurting sales...
I'd like to stick with brand A or X since they offer soft core processors.
FPGA's by their very nature are low power.. provided you don't clock them fast.
The idea would be to build something like Intel's Speed step into it.. so it slows down or even freezes when not needed. you will want a DPLL version that can have the clock multiplied by more than 2 for this. The DPLL can't be changed without stoppage.. but there are clock muxes too .. so you can clean switch while you change a DPLL.
Ray or Austin might know better about doing this.. I've never tried it.
Maybe even look at a device that uses quadrant clocks instead of global clocks.. but that would limit area to 1/4 of the device per clock. but a fast clock isn't spread over the entire device then (am not sure how much affect this would have on power).
Maybe look at a small coolrunner to handle clock management / power control.
Then start using slow clocks where you don't need speed.. and only fast where critical. You should find the power reduction impressive compared to a DSP. But as with anything.. the higher the clock... the higher the power.. so that's your biggest enemy. If you can't reduce the clock.. then IMO low power will never exist with current silicon.
Next pick you interfaces wisely. Don't use high power interfaces unless absolutely nessassary. And even then revaluate first.
Then pick you IO / CORE / AUX voltages If they are low then you can reduce power... I'm not sure if you can get them to all run of a single battery's voltage.. not using a regulator will save you big time on a power conscious design. failing that... use an ultra high efficient PSU to get your supply voltages from the battery. It will probably be one of the biggest looses power wise.
The last thing is don't choose a device bigger than you need. Silicon area is equates to power.
There is an entire science devoted to low power. And I'm sure I don't know much about it too :-)
There are two issues here: while operating, what is the allowed power budget, and while idling what is the allowed power budget?
Some devices just sit there more that 90% of the time doing nothing (like a software defined handheld radio). Other designs are running
100% of the time.
FPGAs have more leakage current (static current) than a ASSP (like a DSP uC), and thus are not optimal for designs where you want long battery life.
FPGAs are very efficient for doing the work (dynamic power), but high clock speeds means lots of power. Better to make the algorithm highly parallel, and lower the clock rate as much as possible.
Typical ratios for DSP vs FPGA are 80:1 speed up possible if you use a FPGA instead of a DSP. You can use this in reverse, in other words, slow down the 300 MHz DSP clock by a factor of 80 when you implement the algorithm in a FPGA (3.75 MHz for the same 'work').
The LX25 Virtex 4 is ~ 40 mA static leakage at room temp at 1.2 volts. The DSP48 blocks (one 18X18 multiply-accumulate) are 3 to 9 mW/MHz (depending on how much interconnect you use to make your filters).
Reconfiguration can be used to reprogram the device to do different jobs at different times, so a smaller part can do the job of a larger part, saving static power.
Aust> I am working on an instrument that currently uses a 300 MHz TI dual-
Simon, I guess it's been a while since you checked out the quiescent supply currents for the latest parts? For example, worst case Iccintq for the smallest V2PRO (XC2VP2) is 300mA. That's about 20 hours on a NiMH D cell. Typical is 20mA, but no-one would design with typical figures, would they? BTW, anyone know why there's such a big difference from 'typical' to 'max' figures? Does it depend on the configuration used in the part? Cheers, Syms.
Hi Austin, Question. Why does a large slow machine use more power than a small fast one? Cheers, Syms. p.s. I think the algorithm uses more or less the same power whichever way you go, so I always go small and fast to use a smaller part. Product of size and speed and all. I guess that's not good for Xilinx's sales though? Just kidding! ;-)
Make sure you check the latest datasheet, as we used to state all leakages at 100C worst case (theoretical) silicon. We now state what we see from the process control sampling over all actual process corners.
The reason for the leakage is source drain leakage across the smallest geometry transistors. Since we do have a lot of transistors, we have to be very careful to use the leakiest versions only where needed for speed, and use the higher Vt transistors for non-speed paths and circuits (like the memory cells).
One can select for the lowest current devices (which will also be the slowest speed devices), but that is a bad business model, as getting slow parts regularly is not something you necessarily want!
As geometries shrink, leakage increases (per sq-micron). As well, process variations also increase, so there may be a larger variation in the latest generations than in earlier generations for both typical and maximum numbers.
So the typ of 20 mA for a 2VP2 at room temperature is just that, typical process. The max at 300 mA at 100C is the fastest corner part/process number at the hottest temperature.
The current at 85C would be about 2.5X the current at 25C (both from simulations and data). So, the same part would be typically 20 mA at room, and 50 mA at 85C.
There is a small variation with pattern. Not large enough to matter (when compared to process variations).
V4 has a low static (leakage) current (much much lower than other 90nm ICs) because of the triple oxide process we used. So the memory cells are all 0.13 micron, and the same as the V2P generation (in terms of leakage).
If you are interested in a specific part, I could go see where the process is currently running, and provide you with data.
Austin, Thanks for that, it's much clearer now. Of course, as Hal also says, the temperature makes a big difference. I seem to recall you've posted along these lines before, sorry to make you repeat yourself. I'm looking forward to when the V4 datasheet gets filled in. Until then, I'll now use the leakiest parts I buy in either the fastest circuits I design or the ones used in fridges! ;-) Best, Syms.
You should clarify how much usage, or up time, each block is expecting.
Low power is not a direction FPGAs are heading, see the values in this thread of 20 or 40mA typical, 2.5x multiplier for 85'C Tj (thermal run-away anyone :)
Wider supply specs are common in uC, but we may start to see this in FPGA data : they must have some lower RAM_Vcc, which is the Min to keep CONFIG, but at very low/stopped clock speeds, and then the higher operate Vcc.
Austin: Any numbers on a Config_Keep Vcc (no Clock), and the Static Icc at that operate point ?
This is the same as RUN/IDLE in uC designs. For longest battery life, expect to use a good Low Power uC for operator interface, system management, and run the higher power stuff only when you have to.
The Altera guy told you right. The FPGA market is driven by density which requires the latest processing geometries, meaning the smallest. The last generation or two have started to ramp up the quiescent power to a point where there is little chance of having a "low power" FPGA any time in the future. Any new low power devices will only be "low" in relative terms.
If you want to consider an FPGA, look to the older families. The Altera ACEX parts are much lower power than the newer stuff, at least when you are not clocking them. You will have to figure out how large your design will be to determine the dynamic power.
If there are down times for the FPGA processing, would it be possible to power the FPGA off while keeping the user interface running? The FPGA can be reconfigured very quickly so that the user would not be able to notice it. That is something I am doing on our boards, power to the DSP and power hog FPGA are dropped to put the board in a low power mode where just a power controller MCU and an ACEX FPGA are running. This puts power down to < 10 mW and yet the board can respond to external command to power back up within a few 10's of mS.
Rick "rickman" Collins
We can keep the memory contents of the 4VLX25 all the way down to where the configuration logic recognizes a power down condition (runs around ~0.6 V).
Now, to be sure, we have not characterized everything down that far (0.6V), but we did do all characterization for functionality tests from
1.0V to 1.4V, so we know for sure we are safe inside this region (memory contents stay). If someone had a killer app that needed beaucoup parts, we would consider binning for lower numbers.
Some people are considering operating at the 1.2V nominal, and then 'sleeping' at 1.0V. The sleeping is just all clocks stopped (disabled).
Static current is about half as much compared to 1.2V. So let us say you were at 100 mA at 1.2V, that takes you down to maybe ~55mA at 1.0V.
60 mA for 10 hours is 600 mA-Hr, which is not so bad from a power point of view in a battery operated device. With the 1V, that is 600mW-Hr.
AA NIMH batteries are ~ 2000 mA-Hr (1.2V) which is pretty close to 2000 mW-Hr. So with 6 of these, and a good 90% efficient switching power supply, you could have ~10,000 mW-Hr of power.
Given that you have to do something some of the time, you then have to go to full 1.2V ON, and then do something useful. That will then make the power jump up to something a bit larger (depending on what you are doing). Let us suppose you allow yourself 1 ampere in the work hard mode, or 1200 mW per hour when doing something.
Then you can figure out how much time you can be doing something, vs sleeping.
If it is a handheld SDR radio, there is also a 5W transmitter (typical), so you have another 10,000 mW per hour of talk time (assuming a reasonably efficient transmitter).
There is also Vccaux (Iccaux) at 2.5V, and Vcco at ??V to consider as well.
Sounds like that could be well worth the effort. ( and maybe even 0.75V ? )
Only some devices have Vccaux - can that be removed, or does it need to be reduced ? Vcco I presume can be removed on selected banks, if you realled needed to, but the Static Icc on IO cells should be very low, as they are relatively few - correct ?
Forget a V2PRO... unless you need a power PC... there are far cheaper options to get a processor.
I also never suggested using bleeding edge... if you pick an 'older part' you will find the static current better... it just won't have the same capability as the modern 90 nm parts.. although cyclone (cough cough) seem to have a lower quiescent current 12mA - 80 mA.. but they probably cheated to get that.
And even tho A or X seems good what about Q ? Quicklogic Eclipse is a low power (not so) FPGA .. so they might be via OTP... so you prototype with RAM based... but you can't beat the 22 - 250 uA quiescent current... and only 100mA at 100Mhz.
Don't forget the option of powering down when not in use, use a coolrunner to turn the FPGA off if necessary / possible just don't forget to shut down I/O too.. or the saving will be killed by protection diodes. Older FPGA's have smaller configurations and can be programmed fast if you externally clock them.
And yea.. design to typical.. select of test even :-) unless your running at -20 or +60C .. but at 0C you NiMH battery life will be half that at 20C too..
Then pick a better battery... heard of lithium ion? :-) You might also want to watch the D cells.. often the are a 'C' cell in side a cardboard wrapper. There are also special 'radio modeller' NiCAD's that have rather nice mAH ratings... designed for electric cars and planes.
I have a battery pack here good for 600mA hours @ 8.4V... not much bigger than a D cell.