Hi, I'm looking for advice to implement on my FPGA (Xilinx SPARTAN 3A) a VHDL interface with an external COLDFIRE processor. Due to hardware considerations (not mine) I need to use 9 bits of address and 16 bits of datas, The following signals are available on my incoming pinout : TA, TEA, CS1, IRQ1 and R/W.
Has anybody a clue where I can get some VHDL/Verilog code to help me?
Thanks in advance Dargo
Your question is a little like asking, "How long is a piece of string?" The interface depends on how you want it to work and exactly what you want to do with it. If you want to provide a memory mapped register interface, the code will use the address lines to select the register and you will need a signal to indicate that the FPGA is being addressed. R/W will be used to distinguish a read from a write. The IRQ can be used to signal from the FPGA to the CPU that something has happened that the CPU needs to check the FPGA.
The details of the code will depend on the bus cycle of your processor. Do you understand how the coldfile external bus cycle works?
Rick
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