We have a design with master PCI DMA in 64 bits. This design implements the xilinx PCI 64/32 bits IP. The problem is that our board should be plugged in various versions of the PCI bus ( 64 bits/ 66 Mhz and 32 bits/ 33 mhz, 32 bits / 66 Mhz ).
My question is : Is the IP abble to transparently handle the fact that the board is plugged in a 32 or 64 bit PCI slot ?
The goal is to have only one design that feeds the PCI master DMA section with 64 bits data whether the bus is 32 or 64 bits wide.
What are the limitations with this IP ? Are there specifics configuration or design stuffs to add ?
Thanks for your feedbacks.