I use Xilinx ISE webpack 6.1 sp 2, and a spartanII/e xc2s50e.
In my project I use the signals clk_in and clk_out. The frequency of clk_out can be half of clk_in one, or can be equal to clk_in. clk_out is the "official" clock that goes to the rest of fpga.
Now I use clk_out = clk_in/2, and I placed clk_in in GCLK pin using constrain.
I wrote: clk_out