I use Xilinx ise web pack 6.1 sp 2.
In my project I have a signal that is used as clock in only one flip flop. I have a constrain that place this signal on a generic iob.
in the map process I obtain the following error: Using target part "2s50eft256-6". ERROR:MapLib:93 - Illegal LOC on IPAD symbol "din" or BUFGP symbol "din_0_BUFGP" (output signal=din_0_BUFGP), IPAD-IBUFG should only be LOCed to GCLKIOB site.
How can I force this signal to be placed in a non-GCLK pin?
thanks