Hi.
I have found "CAPTURE SITE" viewing Virtex die in FPGA editor. (down-left corner of die). The site has two inputs only (clk,cap).
I think that the "CAPTURE" belongs to JTAG functionality, but I am not sure. I can't find any record of the unit (at Xilinx site).
Does somebody know the goal of this unit? (I've find explanation about similar units "RPCILOGIC,LPCILOGIC" in the group only).
Thanks, Sergey.