ISE 5.2 to 6.1

Nov 10, 2003 6 Replies
C

I installed ISE 6.1 with the service pack and my Spartan IIe design that worked fine under 5.2 no longer works in the timing simulation in 6.1. Also, the number of Slices used increased by 10% as well as the TBUFS. I have fiddled with almost every combination of options in the synth, map, and par to try and recreate the better results I had in ISE 5.2. I talked to Xilinx and they just told me to fiddle with the parameters some more. Has anyone else had similar problems migrating a project from 5.2 to 6.1?



Regards, Colin


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M

Hi,

I was using ISE5.1i. Now i moved to ISE6.1i

From timing perspective, ISE6.1i gives excellent timings compared to ISE5.1i

Almost 7 Plus MHz improvement for the same constraint,Options and ofcourse same design :-)

Regards, Muthu

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G

Hi, In my experience, when I have to move from a release to another of the ISE, I prefer to create a new project and reuse only the vhdl file and the ucf file. Sometimes there are a strange incompatibility from the release that can generate strange behaviour.

By Giuseppe

"colin hankins" ha scritto nel messaggio news:kzCrb.14571$Zb7.8816@fed1read01...

Also,

par

Xilinx

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J

Yes, there has been discussion on this group regarding this "phenomenon." I have a design that lost about 10% in timing going to

6.1 and that was with heavy use of timing constraints and area constraints. I ended up having to hand place individual LUTs (which also means I lost many of the benefits of synthesis). I wasn't very happy.

I've gone back to 5.2 on some of my projects. 6.1 on a few, but with this kind of track record, I don't have much faith in 6.1. If it ain't broke...

Jake

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K

Also,

par

Xilinx

Even worse, I have fatal errors in synthesis of pipelined LUT multipliers which worked fine in 5.2 Talked to Xilinx and got the same useless answer...

Hopefully, someone will stumble on a solution, or Xilinx will fix it in a service pack. If not, we'll be stuck on 5.2 ;(

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M

I'd be happy to be stuck with 5.2 as I seem to be stuck with 4.2. Trying to port a 4.2 design to 5.1, 5.2, and 6.1 results in failure. The failure occurs attempting to synthesize the simple top level schematic.

Marc

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