I am write and read from a text file using vhdl. I am using quartus4.0 to compile and simulate. when I compile the code below, it said that the writeline, write functions are not synthesis, which is correct. Then when I simulate using simulator tools, it does not work, and nothing get written to the "test_1.txt".
Did anyone try to do this in Quartus before? and what is the problems in my code?
Thank you in advance for ur time and effort, John.
Library IEEE; use ieee.std_logic_1164.all;
entity test_1_wrrd is
generic( Input_File : string := "test_1.txt" );
port ( a : in std_logic; -- clk : in std_logic; b : out std_logic; s : in std_logic ); end entity test_1_wrrd;
architecture beh of test_1_wrrd is begin
Process(a, s) file p_file : text open write_mode is Input_File ; Variable l : Line;
Begin if s = '1' then b