DSP - ElectronDepot

Hi, I am working on a project of a dc-dc converter wherein we require to generate hardware implementations from z-transform equations. My fellow researchers are using system generator and simulink to generate hardware implementation from the z-transform equations on FPGAs.(that is they get differential equation in terms of z^-1, z^-2 etc. for e.g. they realize 1.8*z^-2 using a constant element, a multiplier and two Z^-1 delay elements) However, I need to implement those z-transform equations on CPLDs. I wonder if i could use system generator for that. but nowhere in xilinx website or system generator documentation is there any mention of CPLDs. everywhere it says that DSP implementation can be done by system generator on FPGAs. however one thing that intrigues me is that if all system generator does is to generate vhdl code for the hardware implementation from the z-transform equation(xilinx blocks) then why can't we use that vhdl code and generate the same hardware on cpld. if someonce could throw any light on this issue i'd be highly obliged. or if you know someone who you think might be able to guide me on this please pass me his email address. sincere regards, vishal shah

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I think you'd probably be better off just writing the HDL directly from = your Z-transforms. It would be faster and you'd have more control. But = that's a different matter.

If you look at the HDL you can tell it it will port to CPLDs. If it is = just RTL source, it should port fine. Most likely, though, it will = instantiate a lot of primitives that aren't available on a CPLD, which = may be another reason to write the source directly. I can't imagine = that SystemGenerator code is highly portable, or it would be portable to = a competitor's part.

The main problem you are going to have, though, is that the CPLD just = won't have enough gates to do what you want. The Virtex-II parts have = embedded multipliers for DSP operations, and the other families have = families have hardware to make implementing multipliers easier. = Multipliers may not be feasible on a CPLD. You might only have room for = the smallest of operations.

however one thing that intrigues me is that if all system generator=20 does is to generate vhdl code for the hardware implementation from=20 the z-transform equation(xilinx blocks) then why can't we use that=20 vhdl code and generate the same hardware on cpld.=20

if someonce could throw any light on this issue i'd be highly obliged. =

or if you know someone who you think might be able to guide me on=20 this please pass me his email address.=20

sincere regards,=20 vishal shah