I am using Mathworks Simulink and Xilinx ISE tools for digital designs related to wireless communications. People who are using this design flow are requested to answer/ share their experience. The descreptionof my problem is as follows:
I am using Xilinx black box in a Simulink Model and am using my VHDL code for its hardware implementation. The idea is to use the Simulink model as a test bed for checking my hardware model for Wireless/ DSP based algos. I have successfully checked the behavioral simulation of my Code using HDL Co-simulation. The next stage in my design flow is to take it to the target Xilinx FPGA device and complete synthesis and place and route. At this stage, I want to go back to my Simulink model and use it to test my placed and routed model (now available in the form of flat netlist with Xilinx Simprims and SDF file (timing info file). I am able to verify post PAR outside Simulink by using my own test bench and controlling the clock myself in it.
I want to do the same with the simulink model and check the results in simulink environment. Now the problem is:1) How to control the clock that is generated automatically, whenever the simulation is started from within simulink. I dug into the files that are generated by Simulink for making a simulation model for HDL Co simulation, and found that it generated the clock with period 6.25 ns always. Question is that is it possible to change this clock period.
2) How to link the SDF file in the simulation model that is generated from within Simulink for HDL Co simulation, for doing Post PAR simulation with simulink data.3) If all above is not possible, then is there any way to make a test bench with the simulink generated data (the data that is available right after the gateway blocks). If this is possible then I can test my model outside simulink in modelsim environment.