Matlab/Simulink - System Generator HDL Co-Simulation

I am using Mathworks Simulink and Xilinx ISE tools for digital designs related to wireless communications. People who are using this design flow are requested to answer/ share their experience. The descreptionof my problem is as follows:

I am using Xilinx black box in a Simulink Model and am using my VHDL code for its hardware implementation. The idea is to use the Simulink model as a test bed for checking my hardware model for Wireless/ DSP based algos. I have successfully checked the behavioral simulation of my Code using HDL Co-simulation. The next stage in my design flow is to take it to the target Xilinx FPGA device and complete synthesis and place and route. At this stage, I want to go back to my Simulink model and use it to test my placed and routed model (now available in the form of flat netlist with Xilinx Simprims and SDF file (timing info file). I am able to verify post PAR outside Simulink by using my own test bench and controlling the clock myself in it.

I want to do the same with the simulink model and check the results in simulink environment. Now the problem is:

1) How to control the clock that is generated automatically, whenever the simulation is started from within simulink. I dug into the files that are generated by Simulink for making a simulation model for HDL Co simulation, and found that it generated the clock with period 6.25 ns always. Question is that is it possible to change this clock period.

2) How to link the SDF file in the simulation model that is generated from within Simulink for HDL Co simulation, for doing Post PAR simulation with simulink data.

3) If all above is not possible, then is there any way to make a test bench with the simulink generated data (the data that is available right after the gateway blocks). If this is possible then I can test my model outside simulink in modelsim environment.



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Hi Mukesh

Here are some answers to your questions:

1) I think you are referring to the timing constraints that Sysgen is creating during generation. The actual clock will be provided from an external source, either a from a testbench stimulus, or in hardware from some oscillator feeding the clock pin. In Sysgen you specify how the Simulink sample period relates to the hardware clock, then Sysgen writes timing constraints based on what you specify. The purpose of the timing constraints are to ensure that the design will work properly for a given clock frequency. You can change the clock source to be of any frequency that you want, but to be sure that the design will work properly it is a good idea to test the design in a timing simulation using constraints specific to the desired operating frequency. If you set up a variable in Simulink that represents your sample period, then it will be very easy to re-define the variable in Matlab which will update the design to work at different sample rates. Re-generating the design will then write out new timing constraints, or you can directly modify the constraints in the .XCF file that is written into the project directory.

2) Simulink is only a behavioral simulation environment. The HDL Co-Sim that is done in the Simulink environment will be a behavioral simulation. If you want to use SDF information then you will need to do timing simulations outside of Simulink. The good news is that Sysgen will automatically create a testbench for you that can be used for timing simulations. This answers your question below....

3) Yes. When you double click on the Sysgen Token to generate, there is an option to tell Sysgen to generate a testbench. This takes any data that is coming into a gateway in block and writes the data into a text file. This text file is then read in by a VHDL testbench so the same inputs that are driving the Simulink design will now be used as stimulus when simulations are done using a standard HDL simulation tool.

If you have more questions about this then I encourage you to open a case with Xilinx's hotline:

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Best Regards, Elliot

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Elliot Schei

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