Do Synplify DSP and Accelchip support multiple clock domains?

Question as subject.

Can't find anywhere that explicitly says one way or the other so was wondering if anyone here knows?

Thanks for your time,

Dave

Reply to
Dave
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Synplify DSP does indeed support multi-rate systems. It utilizes the sample rate capabilities that are native in the Simulink environment from The MathWorks. Synplify DSP fully understands all of a users sample rate designations, and will exploit this information to create an optimal implementation.

All the designer needs to do is specify the sample rate on the design inputs. This can be done explicitly, or inherited from the signals that drive the system. Sample rates are then propagated automatically through all blocks, changing when requested through an upsample or downsample instance. All sample rates domains are derived automatically from this infrastructure, and Synplify DSP infers the required interface between sample domains during hardware implementation. It may even create a multi-rate system from a single-rate specification in order to achieve this most efficient hardware implementation. The goals is to ease the specification process through automation, and relieve the designer from the tedious tasks of system level clock definition and interface specification in a multi-rate design.

Our product overview can be found here:

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A white paper that may be more helpful can be found here:

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I hope this helps. Andrew

Reply to
Andrew_from_Synplicity

Hi Andrew,

Thanks for your answer.

However, I am aware of Synplify DSP's DSP Synthesis capabilities when it comes to inferring efficient structures in multi-rate systems where each sampling domain is an *integer ratio* of the others.

What is not clear from your answer is whether or not Synplify DSP supports multiple *clock* domains where the tools must infer suitable hardware to transfer data reliably from one clock domain to another, unrelated, asynchronous clock domain.

Sorry if this seems pedantic but mutiple sampling rate domains that are integer ratios of one another are a very different design prospect to multiple, unrelated clock domains.

Cheers,

Dave

Reply to
Dave

Hi Dave, Yes. these are very different. To the best of my knowledge, Simulink supports only multi-rate systems that are in some manner synchronous. That is, you really can not model 2 (or more) asynchrounous clock domains in Simulink. As we derive implementations from the Simulink model, Synplify DSP does not, from a single model, allow for asynchronous clock domains during implementation.

If the model had 2 seperate sample rate specifications for 2 completely unrelated datapaths, I think it should be OK. Synplify DSP would create

2 clock ports, that you could define as unrelated in Synplify Pro thru the timing constraints file. However, if the domains at all communicated in the same model, Synplify DSP would not try to synchronize the logic (as it assumed they were synchronously related).

Seperate models could also be put thru Synplify DSP seperately, and hooked up in Synplify Pro with RTL created outside of Simulink/SynplifyDSP.

If you know of any common or good ways to model asynchronous systems in Simulink, please let me know. We'd love to infer that from the Simulink model during Synplify DSP synthesis.

Thanks Andrew

Reply to
Andrew_from_Synplicity

Hi Andrew,

Xilinx SysGen seems to support it using two subsystems as you suggest as a solution.

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Cheers,

Dave

Reply to
Dave

Hello Dave--

The AccelChip DSP Synthesis product uses MATLAB M-files as its input language. MATLAB in general can support multirate systems that are integral fractions of a base rate -- alternatively you could say that MATLAB can be used to model multi-rate systems with the restriction that the clocks must be synchronous and integer multiples of each other.

This can be accomplished with AccelChip using the streaming loop coding style as shown below. In this example the design function "design_func1" runs at the clock frequency, "design_func2" runs at =BD the clock frequency, and "design_func2" runs at 1/3 the clock frequency.

for n =3D 1:NUM_ITER

outdata3 =3D design_func1(indata); % freq

if mod(n,2) =3D 0 outdata2 =3D design_func2(indata); % freq / 2 end;

if mod(n,3) =3D 0 outdata1 =3D design_func3(indata); % freq / 3 end;

end;

With regard to Simulink -- it would be best to check with The MathWorks but to my knowledge there is no need for any integral relationship between rates in Simulink. If you have access to Simulink documentation, just look for the section titled "Modeling and Simulating Discrete Systems."

AccelChip can be used in combination with Xilinx System Generator for DSP. Each subsystem can by synthesized with AccelChip and then assembled in System Generator in order to achieve multiple rates.

Information regarding Xilinx's support for multiple clocks is described at

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7_Section_2.htm

--Eric

Reply to
Eric_at_AccelChip

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