System Generator HDL co-simulatin problem

Oleg,

In Altera DSPBuilder I have found that it is not possible to simulate external VHDL, if I want simulation I have to fill in the black box with equivalent model built out of Simulink _or_ Altera blocks. I would be very interested to know if System Generator supports simulation of external VHDL.

However Matlab and Mentor have a product available that allows running ModelSim VHDL and Verilog simulations from Matlab+Simulink.

I'm also interested to hear your overall experience and satisfaction with SystemGenerator, online or off.

Regards,

-rajeev-

Oleg,

If ModelSim does not open at all usually this is an indication that the ModelSim path is not setup correctly.

If ModelSim does open, failures of this sort can be related to the amount of time required to launch the ModelSim process and for it to get through its startup and to communicate back to Sysgen. The delay can be a function of processor speed, local vs. network installation, licensing issues, etc. Sysgen v6.1 is set to wait to hear from ModelSim for a fixed period of time and if this time is exceeded then this error will be seen in Sysgen.

To improve load time try moving ModelSim to the front of your path and license environment variables.

Later, Chris

Oleg wrote:

Rajeev,

System Generator for DSP now supports HDL Co-Simulation using ModelSim. This allows you to BlackBox your HDL, and bring it into Simulink. When you simulate the design, ModelSim is called by SysGen in order to simulate the HDL.

You can find out more informaiton here.

Later, Chris

Rajeev wrote:

Yes you can simulat imported VHDL > However Matlab and Mentor have a product available that allows running

Yes its good tool but it can only simulat your design. System generator can also (after you simulat your design to make sure it work correctly) implement you design in the FPGA and make a test (simulation) in the hardwar which is caled hardward co-simulation.

Regards