HI, I am seeing a design left from my colleague and I see he set conflicting timing constraints like this, 1) On a 100MHz data path, he used a DCM and set the parameters so that CLKFX runs at 56MHz.\ 2) In UCF, he defined the constraint for CLKFX like this, NET "clk_fx" PERIOD = 27.8 ns HIGH 50 %;
These 2 things conflict with each other, does UCF always takes precedence? That's my guess, but I also see some other conflicting constraints like this, it seems not always this way.
In another words is there any good reason to do design like this? Generate a clock and in UCF override it?
The period for a 56MHz clock is 17.85 ns . If he really wrote 27.8, then it is plain wrong. Or maybe you mistyped the value.
Actually, they do not conflict. Period is the reciprocal of frequency, the time from one rising edge to the next rising edge (or falling to falling). The HIGH 50% just says that the CLKFX is symmetrical, 50% high time, 50% low time. Usually not an issue unless you are using both edges of a clock.
The UCF (and also your design files VHDL/Verilog/Schematic) can all contain both parameters and constraints. Although they look the similar, they behave differently.
As you wrote above (1) there are parameters that set the DCM CLKFX to be 56MHz. unless there are errors in the parameter value, or the input is not really 100MHz, the CLKFX output will be 56MHz.
Parameters specify the operating mode of various functions on the FPGA, as well as the initial conditions of other parts of the FPGA (such as initial value for a flip flop, or ROM contents, or initial RAM contents).
As you wrote above (2) there are timing constraints. These constraints (and there are many variants) are goals being set for the place and route software to meet. They do not affect the logic being built, but do affect how the logic is placed and routed. (There is a special case of signal replication for reducing net loading, but the functional result is the same logic).
In this case, the PERIOD constraint is wrongly telling the router that it can have path delays of up to 27.8ns between synchronous elements that are both clocked by the clk_fx net. The router will stop trying to make these paths any faster, once these paths are less than or equal to 27.8 ns. The design will almost certainly fail.
Constraints that occur in the UCF override constraints that occur in the design files.
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