Hi all, I developed a design in which i need a master clock of 90Mhz, so during synthesis max. freq obtained is 56Mhz and timing is met for global clock of 50Mhz, but timing are not met for 90Mhz. but design is working on board for 90Mhz clcock. In design all lower level module are working above 100 Mhz, but in top module after integarting sub blocks it works around 56 Mhz in synthesis and working at 90Mhz on board. so please tell me what is wrong with this design. Regards J.Ram
- posted
16 years ago