1. Home
  2. Field-Programmable Gate Arrays
  3. Delay insertion in Xilinx Verilog

Delay insertion in Xilinx Verilog

Hello,

I'm trying to force a long logic delay in a Xilinx FPGA using a chain of inverters. However, these seem to get optimised out of the design. Can someone tell me how to specify that certain signals are not to be optimised?

I'm using Xilinx ISE 6.3 and an XC2V250 FPGA.

Regards,

Dave.

Reply to
Dave Roberts
Loading thread data ...

When you say logic delay, do you mean you want to increase delay in the same clock or do you just want to add delays?

For just delays, you can add as many flip-flops as the number of clock-delays you need. But I am guessing you need delay between two registers, right?

I am wondering why do you need such a delay?

Robert.

Reply to
robertncsu

You are exactly right. I'm a researcher doing error control experiments and I need to find a way of making an arbitrary delay between registers. Any ideas how I can do this? Ideally I want to build a 32-bit wide bus between registers where each bit line has approximately the same (long) delay. I want to make a fake critical path.

Regards,

Dave.

Reply to
Dave Roberts

There is some way to keep logic that the compiler is smart enough to discard. I forget how to do it.

How about putting some dummy logic in there? Say an AND gate. Connect the other side of the gate to something like an input pin so the compiler can't outsmart you.

Then go into the floorplanner and adjust the spacing to get the sort of delays you like. Maybe iterate adding more dummy gates.

You might need to put a pipeline register right next to the dummy input to the AND gate to make sure it doesn't become the long path.

--
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.
Reply to
Hal Murray

You should use primitives, and check out "Optimize instantiated primitives". I think you should alos LOC or RLOC the primitives, to have more control over the delay

-- Zara

Reply to
Zara

Use LUT primitives (not gates) to ensure that the tools don't remove them. Also it is possible to get finer-grained delays using carry-chain primitives, but you'll need to do a lot more work to achieve this. Xilinx has an appnote XAPP250 with a reference design in verilog and VHDL. Look at the Verilog module muxdelchain32.v for an example of using carry chain primitives.

Reply to
Gabor

Can you use the DLL to generate a ps clock shift to clock the two registers instead ??

I'm not sure exactly what you are after but you can create arbitrary shifts that way Simon

and

Any

between

I

the

Reply to
Simon Peacock

There's supposed to be a "keep" option that prevents signals from being optimized away. It seems, though, that unless the signal with the "keep" directive is connected to an external pin, it gets optimized away anyway. As long as you have spare pins, you can send the signal to an I/O pin, and then read it back from the same pin. For longer delays, I have used a resistor between two pins, using the capacitance of the input pin as the C of an R*C time constant. You can get delays up to microseconds this way, but I usually use it for delays under 20 ns. This is essential with some interface CPLDs where there is no clock whatsoever except the strobes from the bus.

Jon

Reply to
Jon Elson

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.