Hello!
I'm using the Xilinx XAPP134 for a SDRAM controller. It is quite ok and works in the functional simulation, but I don't manage to make it synthesizeable. There's a special directory in the xapp that is called synth - I suppose this should be the synthesizable source files - but I tried to simulate that and "nearly everything" is red lines. :-(
I'm using Xilinx ISE Webpack 5.2i Service Pack 3 together with Modelsim XE Starter 5.6e.
The source code can directly be downloaded at the Xilinx homepage: ftp://ftp.xilinx.com/pub/applications/xapp/xapp134_vhdl.zip Documentation (but unfortunately not a very good one):
Additionally I changed the xapp in order to only have a data with of 16 bit at the output (while leaving the input and internal part unchanged, so no special change). But I also tried to simulate the original 32bit-version ->
it was the same!
Can somebody help me??? I really don't have any experience in making vhdl models synthesizable - I don't know where to start, what to look at - maybe you also have a kind of tutorial that gives an introduction to "making synthesizable vhdl models" or something similar.
Thank you VERY much!! :-))
Simone