What is the constraint to define the clock skews in XST?

Hi, everybody:

I am using ISE6/XST flow. Now in gate-level simulation I faced setuphold timing error...My clocks are odd because they are gated then fed into a global clock buffer...

Is there any constraints which set the maximum clock uncertainty to all the registers in this clock domain? I need to make P&R to insert buffer or anything to fix the timing check error...

Thanks in advance.

Best Regards, Kelvin